[mips][msa] Implemented fill.d intrinsic.

This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191519 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/IR/IntrinsicsMips.td b/include/llvm/IR/IntrinsicsMips.td
index e90c975bf426d71c57ff666f6086cc139158805b..53e21428bf4ea2311b7189b429ff0b66b76185a7 100644 (file)
--- a/include/llvm/IR/IntrinsicsMips.td
+++ b/include/llvm/IR/IntrinsicsMips.td
@@ -983,6 +983,8 @@ def int_mips_fill_h : GCCBuiltin<"__builtin_msa_fill_h">,
   Intrinsic<[llvm_v8i16_ty], [llvm_i32_ty], [IntrNoMem]>;
 def int_mips_fill_w : GCCBuiltin<"__builtin_msa_fill_w">,
   Intrinsic<[llvm_v4i32_ty], [llvm_i32_ty], [IntrNoMem]>;
+def int_mips_fill_d : GCCBuiltin<"__builtin_msa_fill_d">,
+  Intrinsic<[llvm_v2i64_ty], [llvm_i64_ty], [IntrNoMem]>;
 
 def int_mips_flog2_w : GCCBuiltin<"__builtin_msa_flog2_w">,
   Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty], [IntrNoMem]>;

diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp
index 9af5a28005398c2d45ecf197b200062eb6587447..b05ab343413f9a2f4bea85d8cc538af058829c28 100644 (file)
--- a/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -1325,15 +1325,17 @@ SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
                        Op->getOperand(2));
   case Intrinsic::mips_fill_b:
   case Intrinsic::mips_fill_h:
-  case Intrinsic::mips_fill_w: {
+  case Intrinsic::mips_fill_w:
+  case Intrinsic::mips_fill_d: {
     SmallVector<SDValue, 16> Ops;
     EVT ResTy = Op->getValueType(0);
 
     for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i)
       Ops.push_back(Op->getOperand(1));
 
-    return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0],
-                       Ops.size());
+    // If ResTy is v2i64 then the type legalizer will break this node down into
+    // an equivalent v4i32.
+    return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size());
   }
   case Intrinsic::mips_flog2_w:
   case Intrinsic::mips_flog2_d:

diff --git a/test/CodeGen/Mips/msa/2r_vector_scalar.ll b/test/CodeGen/Mips/msa/2r_vector_scalar.ll
index 1a468cf24602a6fb54f8e6bc885ad0593d3b8d9f..83d99d71740f11acd2fb1aef3fa6a19381e7fbd9 100644 (file)
--- a/test/CodeGen/Mips/msa/2r_vector_scalar.ll
+++ b/test/CodeGen/Mips/msa/2r_vector_scalar.ll
@@ -17,9 +17,9 @@ entry:
 declare <16 x i8> @llvm.mips.fill.b(i32) nounwind
 
 ; CHECK: llvm_mips_fill_b_test:
-; CHECK: lw
-; CHECK: fill.b
-; CHECK: st.b
+; CHECK-DAG: lw [[R1:\$[0-9]+]],
+; CHECK-DAG: fill.b [[R2:\$w[0-9]+]], [[R1]]
+; CHECK-DAG: st.b [[R2]],
 ; CHECK: .size llvm_mips_fill_b_test
 ;
 @llvm_mips_fill_h_ARG1 = global i32 23, align 16
@@ -36,9 +36,9 @@ entry:
 declare <8 x i16> @llvm.mips.fill.h(i32) nounwind
 
 ; CHECK: llvm_mips_fill_h_test:
-; CHECK: lw
-; CHECK: fill.h
-; CHECK: st.h
+; CHECK-DAG: lw [[R1:\$[0-9]+]],
+; CHECK-DAG: fill.h [[R2:\$w[0-9]+]], [[R1]]
+; CHECK-DAG: st.h [[R2]],
 ; CHECK: .size llvm_mips_fill_h_test
 ;
 @llvm_mips_fill_w_ARG1 = global i32 23, align 16
@@ -55,8 +55,32 @@ entry:
 declare <4 x i32> @llvm.mips.fill.w(i32) nounwind
 
 ; CHECK: llvm_mips_fill_w_test:
-; CHECK: lw
-; CHECK: fill.w
-; CHECK: st.w
+; CHECK-DAG: lw [[R1:\$[0-9]+]],
+; CHECK-DAG: fill.w [[R2:\$w[0-9]+]], [[R1]]
+; CHECK-DAG: st.w [[R2]],
 ; CHECK: .size llvm_mips_fill_w_test
 ;
+@llvm_mips_fill_d_ARG1 = global i64 23, align 16
+@llvm_mips_fill_d_RES  = global <2 x i64> <i64 0, i64 0>, align 16
+
+define void @llvm_mips_fill_d_test() nounwind {
+entry:
+  %0 = load i64* @llvm_mips_fill_d_ARG1
+  %1 = tail call <2 x i64> @llvm.mips.fill.d(i64 %0)
+  store <2 x i64> %1, <2 x i64>* @llvm_mips_fill_d_RES
+  ret void
+}
+
+declare <2 x i64> @llvm.mips.fill.d(i64) nounwind
+
+; CHECK: llvm_mips_fill_d_test:
+; CHECK-DAG: lw [[R1:\$[0-9]+]], 0(
+; CHECK-DAG: lw [[R2:\$[0-9]+]], 4(
+; CHECK-DAG: ldi.b [[R3:\$w[0-9]+]], 0
+; CHECK-DAG: insert.w [[R3]][0], [[R1]]
+; CHECK-DAG: insert.w [[R3]][1], [[R2]]
+; CHECK-DAG: insert.w [[R3]][2], [[R1]]
+; CHECK-DAG: insert.w [[R3]][3], [[R2]]
+; CHECK-DAG: st.w [[R3]],
+; CHECK: .size llvm_mips_fill_d_test
+;