Fix assembling ARM vst2 instructions with double-spaced registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153099 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index ccdadd816691913d999db630b2655f55e75dc51d..911eb132e560ca38b0eec26155a84d82021448af 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -1102,7 +1102,7 @@ public:
   }
 
   bool isVecListDPairSpaced() const {
-    if (!isSingleSpacedVectorList()) return false;
+    if (isSingleSpacedVectorList()) return false;
     return (ARMMCRegisterClasses[ARM::DPairSpcRegClassID]
               .contains(VectorList.RegNum));
   }

diff --git a/test/MC/ARM/neon-vst-encoding.s b/test/MC/ARM/neon-vst-encoding.s
index 2b14d37a5b87178648c690a6219c9c2eb9a71b1d..1f07461d10ce56bfb1df24f66a9d898168915339 100644 (file)
--- a/test/MC/ARM/neon-vst-encoding.s
+++ b/test/MC/ARM/neon-vst-encoding.s
@@ -264,3 +264,7 @@
 @ CHECK: vst1.8        {d4, d5}, [r2]          @ encoding: [0x0f,0x4a,0x02,0xf4]
 @ CHECK: vst1.8        {d4, d5}, [r2]          @ encoding: [0x0f,0x4a,0x02,0xf4]
 @ CHECK: vst1.32 {d4, d5}, [r2]         @ encoding: [0x8f,0x4a,0x02,0xf4]
+
+@ rdar://11082188
+        vst2.8 {d8, d10}, [r4]
+@ CHECK: vst2.8        {d8, d10}, [r4]         @ encoding: [0x0f,0x89,0x04,0xf4]

diff --git a/test/MC/ARM/neont2-vst-encoding.s b/test/MC/ARM/neont2-vst-encoding.s
index 1722f12a00f6c7b0cfab4933b0a8928cfb43104f..b50d8b63c1c26a040e8800dd637670d9df0fc9d1 100644 (file)
--- a/test/MC/ARM/neont2-vst-encoding.s
+++ b/test/MC/ARM/neont2-vst-encoding.s
@@ -101,3 +101,7 @@
   vst4.16      {d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
 @ CHECK: vst4.32       {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf9]
   vst4.32      {d17[0], d19[0], d21[0], d23[0]}, [r0]
+
+@ rdar://11082188
+        vst2.8 {d8, d10}, [r4]
+@ CHECK: vst2.8        {d8, d10}, [r4]         @ encoding: [0x04,0xf9,0x0f,0x89]