Clarify naming and correct conditional so that CMP and CMN instructions get the Rn...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57252 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index a8fe2ea4f19f214a7e6a9d048f9a3564ccb9cad4..13f7903402ee5870d65a451b6d299ecab32637d3 100644 (file)
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -392,14 +392,11 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
 
   // Encode first non-shifter register operand if there is one.
   unsigned Format = TID.TSFlags & ARMII::FormMask;
-  bool isUnary = (Format == ARMII::DPRdMisc  ||
-                  Format == ARMII::DPRdIm    ||
-                  Format == ARMII::DPRdReg   ||
-                  Format == ARMII::DPRdSoReg ||
-                  Format == ARMII::DPRnIm    ||
-                  Format == ARMII::DPRnReg   ||
-                  Format == ARMII::DPRnSoReg);
-  if (!isUnary) {
+  bool hasRnOperand= !(Format == ARMII::DPRdMisc  ||
+                       Format == ARMII::DPRdIm    ||
+                       Format == ARMII::DPRdReg   ||
+                       Format == ARMII::DPRdSoReg);
+  if (hasRnOperand) {
     Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
     ++OpIdx;
   }