void join(LiveInterval &Other,
const int *ValNoAssignments,
const int *RHSValNoAssignments,
- SmallVector<VNInfo*, 16> &NewVNInfo,
+ SmallVectorImpl<VNInfo *> &NewVNInfo,
MachineRegisterInfo *MRI);
/// isInOneLiveRange - Return true if the range specified is entirely in the
void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
- SmallVector<unsigned, 4> &Defs);
- void UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);
+ SmallVectorImpl<unsigned> &Defs);
+ void UpdatePhysRegDefs(MachineInstr *MI, SmallVectorImpl<unsigned> &Defs);
/// FindLastRefOrPartRef - Return the last reference or partial reference of
/// the specified register.
return false;
}
-static bool isReverseVectorMask(SmallVector<int, 16> &Mask) {
+static bool isReverseVectorMask(SmallVectorImpl<int> &Mask) {
for (unsigned i = 0, MaskSize = Mask.size(); i < MaskSize; ++i)
if (Mask[i] > 0 && Mask[i] != (int)(MaskSize - 1 - i))
return false;
///
static bool
CollectAddOperandsWithScales(DenseMap<const SCEV *, APInt> &M,
- SmallVector<const SCEV *, 8> &NewOps,
+ SmallVectorImpl<const SCEV *> &NewOps,
APInt &AccumulatedConstant,
const SCEV *const *Ops, size_t NumOperands,
const APInt &Scale,
// struct. To is the result struct built so far, new insertvalue instructions
// build on that.
static Value *BuildSubAggregate(Value *From, Value* To, Type *IndexedType,
- SmallVector<unsigned, 10> &Idxs,
+ SmallVectorImpl<unsigned> &Idxs,
unsigned IdxSkip,
Instruction *InsertBefore) {
llvm::StructType *STy = dyn_cast<llvm::StructType>(IndexedType);
/// getValueTypePair - Read a value/type pair out of the specified record from
/// slot 'Slot'. Increment Slot past the number of slots used in the record.
/// Return true on failure.
- bool getValueTypePair(SmallVector<uint64_t, 64> &Record, unsigned &Slot,
+ bool getValueTypePair(SmallVectorImpl<uint64_t> &Record, unsigned &Slot,
unsigned InstNum, Value *&ResVal) {
if (Slot == Record.size()) return true;
unsigned ValNo = (unsigned)Record[Slot++];
/// popValue - Read a value out of the specified record from slot 'Slot'.
/// Increment Slot past the number of slots used by the value in the record.
/// Return true if there is an error.
- bool popValue(SmallVector<uint64_t, 64> &Record, unsigned &Slot,
+ bool popValue(SmallVectorImpl<uint64_t> &Record, unsigned &Slot,
unsigned InstNum, Type *Ty, Value *&ResVal) {
if (getValue(Record, Slot, InstNum, Ty, ResVal))
return true;
}
/// getValue -- Like popValue, but does not increment the Slot number.
- bool getValue(SmallVector<uint64_t, 64> &Record, unsigned Slot,
+ bool getValue(SmallVectorImpl<uint64_t> &Record, unsigned Slot,
unsigned InstNum, Type *Ty, Value *&ResVal) {
ResVal = getValue(Record, Slot, InstNum, Ty);
return ResVal == 0;
/// getValue -- Version of getValue that returns ResVal directly,
/// or 0 if there is an error.
- Value *getValue(SmallVector<uint64_t, 64> &Record, unsigned Slot,
+ Value *getValue(SmallVectorImpl<uint64_t> &Record, unsigned Slot,
unsigned InstNum, Type *Ty) {
if (Slot == Record.size()) return 0;
unsigned ValNo = (unsigned)Record[Slot];
}
/// getValueSigned -- Like getValue, but decodes signed VBRs.
- Value *getValueSigned(SmallVector<uint64_t, 64> &Record, unsigned Slot,
+ Value *getValueSigned(SmallVectorImpl<uint64_t> &Record, unsigned Slot,
unsigned InstNum, Type *Ty) {
if (Slot == Record.size()) return 0;
unsigned ValNo = (unsigned)decodeSignRotatedValue(Record[Slot]);
static void WriteMDNode(const MDNode *N,
const ValueEnumerator &VE,
BitstreamWriter &Stream,
- SmallVector<uint64_t, 64> &Record) {
+ SmallVectorImpl<uint64_t> &Record) {
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
if (N->getOperand(i)) {
Record.push_back(VE.getTypeID(N->getOperand(i)->getType()));
BitstreamWriter &Stream) {
bool StartedMetadataBlock = false;
SmallVector<uint64_t, 64> Record;
- const SmallVector<const MDNode *, 8> &Vals = VE.getFunctionLocalMDValues();
+ const SmallVectorImpl<const MDNode *> &Vals = VE.getFunctionLocalMDValues();
for (unsigned i = 0, e = Vals.size(); i != e; ++i)
if (const MDNode *N = Vals[i])
if (N->isFunctionLocal() && N->getFunction() == &F) {
/// instruction ID, then it is a forward reference, and it also includes the
/// type ID. The value ID that is written is encoded relative to the InstID.
static bool PushValueAndType(const Value *V, unsigned InstID,
- SmallVector<unsigned, 64> &Vals,
+ SmallVectorImpl<unsigned> &Vals,
ValueEnumerator &VE) {
unsigned ValID = VE.getValueID(V);
// Make encoding relative to the InstID.
/// pushValue - Like PushValueAndType, but where the type of the value is
/// omitted (perhaps it was already encoded in an earlier operand).
static void pushValue(const Value *V, unsigned InstID,
- SmallVector<unsigned, 64> &Vals,
+ SmallVectorImpl<unsigned> &Vals,
ValueEnumerator &VE) {
unsigned ValID = VE.getValueID(V);
Vals.push_back(InstID - ValID);
}
static void pushValue64(const Value *V, unsigned InstID,
- SmallVector<uint64_t, 128> &Vals,
+ SmallVectorImpl<uint64_t> &Vals,
ValueEnumerator &VE) {
uint64_t ValID = VE.getValueID(V);
Vals.push_back(InstID - ValID);
}
static void pushValueSigned(const Value *V, unsigned InstID,
- SmallVector<uint64_t, 128> &Vals,
+ SmallVectorImpl<uint64_t> &Vals,
ValueEnumerator &VE) {
unsigned ValID = VE.getValueID(V);
int64_t diff = ((int32_t)InstID - (int32_t)ValID);
/// WriteInstruction - Emit an instruction to the specified stream.
static void WriteInstruction(const Instruction &I, unsigned InstID,
ValueEnumerator &VE, BitstreamWriter &Stream,
- SmallVector<unsigned, 64> &Vals) {
+ SmallVectorImpl<unsigned> &Vals) {
unsigned Code = 0;
unsigned AbbrevToUse = 0;
VE.setInstructionID(&I);
const ValueList &getValues() const { return Values; }
const ValueList &getMDValues() const { return MDValues; }
- const SmallVector<const MDNode *, 8> &getFunctionLocalMDValues() const {
+ const SmallVectorImpl<const MDNode *> &getFunctionLocalMDValues() const {
return FunctionLocalMDs;
}
const TypeList &getTypes() const { return Types; }
void LiveInterval::join(LiveInterval &Other,
const int *LHSValNoAssignments,
const int *RHSValNoAssignments,
- SmallVector<VNInfo*, 16> &NewVNInfo,
+ SmallVectorImpl<VNInfo *> &NewVNInfo,
MachineRegisterInfo *MRI) {
verify();
}
void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
- SmallVector<unsigned, 4> &Defs) {
+ SmallVectorImpl<unsigned> &Defs) {
// What parts of the register are previously defined?
SmallSet<unsigned, 32> Live;
if (PhysRegDef[Reg] || PhysRegUse[Reg]) {
}
void LiveVariables::UpdatePhysRegDefs(MachineInstr *MI,
- SmallVector<unsigned, 4> &Defs) {
+ SmallVectorImpl<unsigned> &Defs) {
while (!Defs.empty()) {
unsigned Reg = Defs.back();
Defs.pop_back();
BitVector &PhysRegDefs,
BitVector &PhysRegClobbers,
SmallSet<int, 32> &StoredFIs,
- SmallVector<CandidateInfo, 32> &Candidates);
+ SmallVectorImpl<CandidateInfo> &Candidates);
/// AddToLiveIns - Add register 'Reg' to the livein sets of BBs in the
/// current loop.
BitVector &PhysRegDefs,
BitVector &PhysRegClobbers,
SmallSet<int, 32> &StoredFIs,
- SmallVector<CandidateInfo, 32> &Candidates) {
+ SmallVectorImpl<CandidateInfo> &Candidates) {
bool RuledOut = false;
bool HasNonInvariantUse = false;
unsigned Def = 0;
return true;
for (unsigned i = BackTrace.size(); i != 0; --i) {
- SmallVector<unsigned, 8> &RP = BackTrace[i-1];
+ SmallVectorImpl<unsigned> &RP = BackTrace[i-1];
if (RP[RCId] + Cost >= Limit)
return true;
}
// Update register pressure of blocks from loop header to current block.
for (unsigned i = 0, e = BackTrace.size(); i != e; ++i) {
- SmallVector<unsigned, 8> &RP = BackTrace[i];
+ SmallVectorImpl<unsigned> &RP = BackTrace[i];
for (DenseMap<unsigned, int>::iterator CI = Cost.begin(), CE = Cost.end();
CI != CE; ++CI) {
unsigned RCId = CI->first;