Add a blurb about the new LSR.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102126 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/docs/ReleaseNotes.html b/docs/ReleaseNotes.html
index f7d666689866340404486446faf1a6252d29636a..82038c1143a8d5bb0b66e446f05965325efc0eaf 100644 (file)
--- a/docs/ReleaseNotes.html
+++ b/docs/ReleaseNotes.html
@@ -657,7 +657,8 @@ it run faster:</p>
     understand assembly files.  This is wired up in llvm-gcc and clang to
     the <tt>-fverbose-asm</tt> option.</li>
 
-<li>New LSR with "full strength reduction" mode.  FIXME: Description?</li>
+<li>New LSR with "full strength reduction" mode, which can reduce address
+    register pressure in loops where address generation is important.</li>
 
 <li>A new codegen level Common Subexpression Elimination pass (MachineCSE)
     is available and enabled by default.  It catches redundancies exposed by