Let the inline asm 'q' constraint match float, and on 64-bit double too.

Fixes PR9602!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134665 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 0dfc3167600ade22fc026b159281b70fab97a021..709b84c1fa22d5b270fc94c236761844fe9b89d0 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -12891,19 +12891,19 @@ X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
       // in the normal allocation?
     case 'q':   // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode.
       if (Subtarget->is64Bit()) {
-       if (VT == MVT::i32)
+       if (VT == MVT::i32 || VT == MVT::f32)
          return std::make_pair(0U, X86::GR32RegisterClass);
        else if (VT == MVT::i16)
          return std::make_pair(0U, X86::GR16RegisterClass);
        else if (VT == MVT::i8)
          return std::make_pair(0U, X86::GR8RegisterClass);
-       else if (VT == MVT::i64)
+       else if (VT == MVT::i64 || VT == MVT::f64)
          return std::make_pair(0U, X86::GR64RegisterClass);
        break;
       }
       // 32-bit fallthrough
     case 'Q':   // Q_REGS
-      if (VT == MVT::i32)
+      if (VT == MVT::i32 || VT == MVT::f32)
        return std::make_pair(0U, X86::GR32_ABCDRegisterClass);
       else if (VT == MVT::i16)
        return std::make_pair(0U, X86::GR16_ABCDRegisterClass);

diff --git a/test/CodeGen/X86/inline-asm-q-regs.ll b/test/CodeGen/X86/inline-asm-q-regs.ll
index 321fd30dbbf18597b07f6b652b89c3dbf66c7b0d..1c8e2f9eec85e19917f12d7b4ffe88eeca3eee4d 100644 (file)
--- a/test/CodeGen/X86/inline-asm-q-regs.ll
+++ b/test/CodeGen/X86/inline-asm-q-regs.ll
@@ -3,8 +3,20 @@
 
        %0 = type { i64, i64, i64, i64, i64 }           ; type %0
 
-define void @t() nounwind {
+define void @test1() nounwind {
 entry:
        %asmtmp = call %0 asm sideeffect "mov    %cr0, $0       \0Amov    %cr2, $1       \0Amov    %cr3, $2       \0Amov    %cr4, $3       \0Amov    %cr8, $0       \0A", "=q,=q,=q,=q,=q,~{dirflag},~{fpsr},~{flags}"() nounwind               ; <%0> [#uses=0]
        ret void
 }
+
+; PR9602
+define void @test2(float %tmp) nounwind {
+  call void asm sideeffect "$0", "q"(float %tmp) nounwind
+  call void asm sideeffect "$0", "Q"(float %tmp) nounwind
+  ret void
+}
+
+define void @test3(double %tmp) nounwind {
+  call void asm sideeffect "$0", "q"(double %tmp) nounwind
+  ret void
+}