// Mips Subtarget features //
//===----------------------------------------------------------------------===//
-def StackAlign16 : SubtargetFeature<"stackalign16", "StackAlignment", "16",
- "Set stack alignment to 16-bytes.">;
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
"General Purpose Registers are 64-bit wide.">;
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
- "Support 64-bit FP registers.", [StackAlign16]>;
+ "Support 64-bit FP registers.">;
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
"true", "Only supports single precision float">;
def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
InMips16Mode(false), InMips16HardFloat(Mips16HardFloat),
InMicroMipsMode(false), HasDSP(false), HasDSPR2(false),
AllowMixed16_32(Mixed16_32 | Mips_Os16), Os16(Mips_Os16), HasMSA(false),
- StackAlignment(8), RM(_RM), OverrideMode(NoOverride), TM(_TM)
+ RM(_RM), OverrideMode(NoOverride), TM(_TM)
{
std::string CPUName = CPU;
if (CPUName.empty())
// HasMSA -- supports MSA ASE.
bool HasMSA;
- unsigned StackAlignment;
-
InstrItineraryData InstrItins;
// The instance to the register info section object
//
static bool useConstantIslands();
- unsigned stackAlignment() const { return StackAlignment; }
+ unsigned stackAlignment() const { return isFP64bit() ? 16 : 8; }
// Grab MipsRegInfo object
const MipsReginfo &getMReginfo() const { return MRI; }