return C;
}
+static Cursor lexPercent(Cursor C, MIToken &Token) {
+ auto Range = C;
+ C.advance(); // Skip '%'
+ while (isIdentifierChar(C.peek()))
+ C.advance();
+ Token = MIToken(MIToken::NamedRegister, Range.upto(C));
+ return C;
+}
+
+static MIToken::TokenKind symbolToken(char C) {
+ switch (C) {
+ case ',':
+ return MIToken::comma;
+ case '=':
+ return MIToken::equal;
+ default:
+ return MIToken::Error;
+ }
+}
+
+static Cursor lexSymbol(Cursor C, MIToken::TokenKind Kind, MIToken &Token) {
+ auto Range = C;
+ C.advance();
+ Token = MIToken(Kind, Range.upto(C));
+ return C;
+}
+
StringRef llvm::lexMIToken(
StringRef Source, MIToken &Token,
function_ref<void(StringRef::iterator Loc, const Twine &)> ErrorCallback) {
auto Char = C.peek();
if (isalpha(Char) || Char == '_')
return lexIdentifier(C, Token).remaining();
+ if (Char == '%')
+ return lexPercent(C, Token).remaining();
+ MIToken::TokenKind Kind = symbolToken(Char);
+ if (Kind != MIToken::Error)
+ return lexSymbol(C, Kind, Token).remaining();
Token = MIToken(MIToken::Error, C.remaining());
ErrorCallback(C.location(),
Twine("unexpected character '") + Twine(Char) + "'");
MIToken Token;
/// Maps from instruction names to op codes.
StringMap<unsigned> Names2InstrOpCodes;
+ /// Maps from register names to registers.
+ StringMap<unsigned> Names2Regs;
public:
MIParser(SourceMgr &SM, MachineFunction &MF, SMDiagnostic &Error,
MachineInstr *parse();
+ bool parseRegister(unsigned &Reg);
+ bool parseRegisterOperand(MachineOperand &Dest, bool IsDef = false);
+ bool parseMachineOperand(MachineOperand &Dest);
+
private:
void initNames2InstrOpCodes();
bool parseInstrName(StringRef InstrName, unsigned &OpCode);
bool parseInstruction(unsigned &OpCode);
+
+ void initNames2Regs();
+
+ /// Try to convert a register name to a register number. Return true if the
+ /// register name is invalid.
+ bool getRegisterByName(StringRef RegName, unsigned &Reg);
};
} // end anonymous namespace
MachineInstr *MIParser::parse() {
lex();
+ // Parse any register operands before '='
+ // TODO: Allow parsing of multiple operands before '='
+ MachineOperand MO = MachineOperand::CreateImm(0);
+ SmallVector<MachineOperand, 8> Operands;
+ if (Token.isRegister()) {
+ if (parseRegisterOperand(MO, /*IsDef=*/true))
+ return nullptr;
+ Operands.push_back(MO);
+ if (Token.isNot(MIToken::equal)) {
+ error("expected '='");
+ return nullptr;
+ }
+ lex();
+ }
+
unsigned OpCode;
if (Token.isError() || parseInstruction(OpCode))
return nullptr;
- // TODO: Parse the rest of instruction - machine operands, etc.
+ // TODO: Parse the instruction flags and memory operands.
+
+ // Parse the remaining machine operands.
+ while (Token.isNot(MIToken::Eof)) {
+ if (parseMachineOperand(MO))
+ return nullptr;
+ Operands.push_back(MO);
+ if (Token.is(MIToken::Eof))
+ break;
+ if (Token.isNot(MIToken::comma)) {
+ error("expected ',' before the next machine operand");
+ return nullptr;
+ }
+ lex();
+ }
+
const auto &MCID = MF.getSubtarget().getInstrInfo()->get(OpCode);
- auto *MI = MF.CreateMachineInstr(MCID, DebugLoc());
+
+ // Verify machine operands.
+ if (!MCID.isVariadic()) {
+ for (size_t I = 0, E = Operands.size(); I < E; ++I) {
+ if (I < MCID.getNumOperands())
+ continue;
+ // Mark this register as implicit to prevent an assertion when it's added
+ // to an instruction. This is a temporary workaround until the implicit
+ // register flag can be parsed.
+ Operands[I].setImplicit();
+ }
+ }
+
+ // TODO: Determine the implicit behaviour when implicit register flags are
+ // parsed.
+ auto *MI = MF.CreateMachineInstr(MCID, DebugLoc(), /*NoImplicit=*/true);
+ for (const auto &Operand : Operands)
+ MI->addOperand(MF, Operand);
return MI;
}
StringRef InstrName = Token.stringValue();
if (parseInstrName(InstrName, OpCode))
return error(Twine("unknown machine instruction name '") + InstrName + "'");
+ lex();
+ return false;
+}
+
+bool MIParser::parseRegister(unsigned &Reg) {
+ switch (Token.kind()) {
+ case MIToken::NamedRegister: {
+ StringRef Name = Token.stringValue().drop_front(1); // Drop the '%'
+ if (getRegisterByName(Name, Reg))
+ return error(Twine("unknown register name '") + Name + "'");
+ break;
+ }
+ // TODO: Parse other register kinds.
+ default:
+ llvm_unreachable("The current token should be a register");
+ }
+ return false;
+}
+
+bool MIParser::parseRegisterOperand(MachineOperand &Dest, bool IsDef) {
+ unsigned Reg;
+ // TODO: Parse register flags.
+ if (parseRegister(Reg))
+ return true;
+ lex();
+ // TODO: Parse subregister.
+ Dest = MachineOperand::CreateReg(Reg, IsDef);
+ return false;
+}
+
+bool MIParser::parseMachineOperand(MachineOperand &Dest) {
+ switch (Token.kind()) {
+ case MIToken::NamedRegister:
+ return parseRegisterOperand(Dest);
+ case MIToken::Error:
+ return true;
+ default:
+ // TODO: parse the other machine operands.
+ return error("expected a machine operand");
+ }
return false;
}
return false;
}
+void MIParser::initNames2Regs() {
+ if (!Names2Regs.empty())
+ return;
+ const auto *TRI = MF.getSubtarget().getRegisterInfo();
+ assert(TRI && "Expected target register info");
+ for (unsigned I = 0, E = TRI->getNumRegs(); I < E; ++I) {
+ bool WasInserted =
+ Names2Regs.insert(std::make_pair(StringRef(TRI->getName(I)).lower(), I))
+ .second;
+ (void)WasInserted;
+ assert(WasInserted && "Expected registers to be unique case-insensitively");
+ }
+}
+
+bool MIParser::getRegisterByName(StringRef RegName, unsigned &Reg) {
+ initNames2Regs();
+ auto RegInfo = Names2Regs.find(RegName);
+ if (RegInfo == Names2Regs.end())
+ return true;
+ Reg = RegInfo->getValue();
+ return false;
+}
+
MachineInstr *llvm::parseMachineInstr(SourceMgr &SM, MachineFunction &MF,
StringRef Src, SMDiagnostic &Error) {
return MIParser(SM, MF, Error, Src).parse();
MIPrinter(raw_ostream &OS) : OS(OS) {}
void print(const MachineInstr &MI);
+ void print(const MachineOperand &Op, const TargetRegisterInfo *TRI);
};
} // end anonymous namespace
void MIPrinter::print(const MachineInstr &MI) {
const auto &SubTarget = MI.getParent()->getParent()->getSubtarget();
+ const auto *TRI = SubTarget.getRegisterInfo();
+ assert(TRI && "Expected target register info");
const auto *TII = SubTarget.getInstrInfo();
assert(TII && "Expected target instruction info");
+ unsigned I = 0, E = MI.getNumOperands();
+ for (; I < E && MI.getOperand(I).isReg() && MI.getOperand(I).isDef() &&
+ !MI.getOperand(I).isImplicit();
+ ++I) {
+ if (I)
+ OS << ", ";
+ print(MI.getOperand(I), TRI);
+ }
+
+ if (I)
+ OS << " = ";
OS << TII->getName(MI.getOpcode());
- // TODO: Print the instruction flags, machine operands, machine mem operands.
+ // TODO: Print the instruction flags, machine mem operands.
+ if (I < E)
+ OS << ' ';
+
+ bool NeedComma = false;
+ for (; I < E; ++I) {
+ if (NeedComma)
+ OS << ", ";
+ print(MI.getOperand(I), TRI);
+ NeedComma = true;
+ }
+}
+
+static void printReg(unsigned Reg, raw_ostream &OS,
+ const TargetRegisterInfo *TRI) {
+ // TODO: Print Stack Slots.
+ // TODO: Print no register.
+ // TODO: Print virtual registers.
+ if (Reg < TRI->getNumRegs())
+ OS << '%' << StringRef(TRI->getName(Reg)).lower();
+ else
+ llvm_unreachable("Can't print this kind of register yet");
+}
+
+void MIPrinter::print(const MachineOperand &Op, const TargetRegisterInfo *TRI) {
+ switch (Op.getType()) {
+ case MachineOperand::MO_Register:
+ // TODO: Print register flags.
+ printReg(Op.getReg(), OS, TRI);
+ // TODO: Print sub register.
+ break;
+ default:
+ // TODO: Print the other machine operands.
+ llvm_unreachable("Can't print this machine operand at the moment");
+ }
}
void llvm::printMIR(raw_ostream &OS, const Module &M) {
projects / oota-llvm.git / commitdiff