Make alignment be in bits, just like size is

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15969 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index 49fd772d2e5dd8c3edc132e665c366445dd273ac..b9c7f5172c4289cc3a13029f0858167e2db915a4 100644 (file)
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -133,7 +133,8 @@ void CodeGenTarget::ReadRegisterClasses() const {
 
 CodeGenRegisterClass::CodeGenRegisterClass(Record *R) : TheDef(R) {
   SpillSize = R->getValueAsInt("Size");
-  SpillAlignment = R->getValueAsInt("Alignment");
+  // FIXME: should convert to bits in all targets.
+  SpillAlignment = R->getValueAsInt("Alignment")*8;
 
   if (CodeInit *CI = dynamic_cast<CodeInit*>(R->getValueInit("Methods")))
     MethodDefinitions = CI->getValue();

diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index 682404ea148334dc9290b75fb6c7c5d7130ff0d9..ef79c35017ecdfbff56a868ddb0589da254ca471 100644 (file)
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -128,7 +128,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
 
     OS << "  struct " << Name << "Class : public TargetRegisterClass {\n"
        << "    " << Name << "Class() : TargetRegisterClass("
-       << RC.SpillSize/8 << ", " << RC.SpillAlignment << ", " << Name << ", "
+       << RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " << Name << ", "
        << Name << " + " << RC.Elements.size() << ") {}\n"
        << RC.MethodDefinitions << "  } " << Name << "Instance;\n\n";
   }