gas accepts xchg <mem>, <reg> as a synonym for xchg <reg>, <mem>.

Add this to the mc assembler, fixing PR8061

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113346 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/AsmParser/X86AsmParser.cpp b/lib/Target/X86/AsmParser/X86AsmParser.cpp
index cddf8ebfc07becdac8c1ea7e566157064e130dfc..58e4554ab03919daecdb0a4ab8325fa92221b260 100644 (file)
--- a/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -753,6 +753,7 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
       PatchedName = "vpclmulqdq";
     }
   }
+  
   Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
 
   if (ExtraImmOp)
@@ -827,6 +828,16 @@ ParseInstruction(StringRef Name, SMLoc NameLoc,
     delete Operands[0];
     Operands[0] = X86Operand::CreateToken("sldtw", NameLoc);
   }
+  
+  // The assembler accepts "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as
+  // synonyms.  Our tables only have the "<reg>, <mem>" form, so if we see the
+  // other operand order, swap them.
+  if (Name == "xchgb" || Name == "xchgw" || Name == "xchgl" || Name == "xchgq")
+    if (Operands.size() == 3 &&
+        static_cast<X86Operand*>(Operands[1])->isMem() &&
+        static_cast<X86Operand*>(Operands[2])->isReg()) {
+      std::swap(Operands[1], Operands[2]);
+    }
 
   return false;
 }

diff --git a/test/MC/AsmParser/X86/x86_64-new-encoder.s b/test/MC/AsmParser/X86/x86_64-new-encoder.s
index 3644147b16795bc229ecc263e30ba8f2eaf0dd01..7992972c988c1a00f48116134724ed7f1a70e818 100644 (file)
--- a/test/MC/AsmParser/X86/x86_64-new-encoder.s
+++ b/test/MC/AsmParser/X86/x86_64-new-encoder.s
@@ -168,3 +168,8 @@ L1:
 // CHECK: jrcxz L1
 // CHECK:   encoding: [0xe3,A]
 
+// PR8061
+xchgl   368(%rax),%ecx
+// CHECK: xchgl        %ecx, 368(%rax)
+xchgl   %ecx, 368(%rax)
+// CHECK: xchgl        %ecx, 368(%rax)