Disable switch lowering for targets based on the selection dag isel,

letting the code generator handle them directly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27539 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp
index 2daaab2d6dca651b373fd28dd46a973d179de030..709669ffd72cc44b4e53ef1f685029e2c757c9f1 100644 (file)
--- a/lib/Target/Alpha/AlphaTargetMachine.cpp
+++ b/lib/Target/Alpha/AlphaTargetMachine.cpp
@@ -81,9 +81,6 @@ bool AlphaTargetMachine::addPassesToEmitFile(PassManager &PM,
   // FIXME: Implement the invoke/unwind instructions!
   PM.add(createLowerInvokePass());
 
-  // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
-
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
@@ -119,9 +116,6 @@ void AlphaJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
   // FIXME: Implement the invoke/unwind instructions!
   PM.add(createLowerInvokePass());
 
-  // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
-
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 

diff --git a/lib/Target/IA64/IA64TargetMachine.cpp b/lib/Target/IA64/IA64TargetMachine.cpp
index 4c7af4147919fca866223147776b35c8e99cd04c..a03bda7e091e9aa9f6284953cfabc353344f1942 100644 (file)
--- a/lib/Target/IA64/IA64TargetMachine.cpp
+++ b/lib/Target/IA64/IA64TargetMachine.cpp
@@ -96,9 +96,6 @@ bool IA64TargetMachine::addPassesToEmitFile(PassManager &PM,
   PM.add(createLowerInvokePass(704, 16)); // on ia64 linux, jmpbufs are 704
                                           // bytes and must be 16byte aligned
 
-  // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
-
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 

diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 60829560a32c1adc85c944d47069338b28cc0b9c..94136a456962b19723798366552af9583c221460 100644 (file)
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -93,9 +93,6 @@ bool PPCTargetMachine::addPassesToEmitFile(PassManager &PM,
   // Clean up after other passes, e.g. merging critical edges.
   if (!Fast) PM.add(createCFGSimplificationPass());
 
-  // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
-
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
@@ -147,9 +144,6 @@ void PPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
   // Clean up after other passes, e.g. merging critical edges.
   PM.add(createCFGSimplificationPass());
 
-  // FIXME: Implement the switch instruction in the instruction selector!
-  PM.add(createLowerSwitchPass());
-
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 

diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 565ccb9bc14984cf10169e4012165686cd2e0574..2b56be2cb9a1779b8d0ea0c71784e72900a33738 100644 (file)
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -72,9 +72,6 @@ bool SparcTargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
   // FIXME: implement the invoke/unwind instructions!
   PM.add(createLowerInvokePass());
 
-  // FIXME: implement the switch instruction in the instruction selector.
-  PM.add(createLowerSwitchPass());
-  
   // Print LLVM code input to instruction selector:
   if (PrintMachineCode)
     PM.add(new PrintFunctionPass());

diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 44877d9b4d1fef00d426f43b202f0062aa8a08b3..b9dea3bcf3059606089689c4bb440bdf321e7b87 100644 (file)
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -36,8 +36,6 @@ namespace {
   cl::opt<bool> DisableOutput("disable-x86-llc-output", cl::Hidden,
                               cl::desc("Disable the X86 asm printer, for use "
                                        "when profiling the code generator."));
-  cl::opt<bool> DisableLowerSwitch("disable-lower-switch", cl::Hidden,
-                                   cl::desc("Disable the LowerSwitch pass"));
   // Register the target.
   RegisterTarget<X86TargetMachine> X("x86", "  IA-32 (Pentium and above)");
 }
@@ -100,10 +98,6 @@ bool X86TargetMachine::addPassesToEmitFile(PassManager &PM, std::ostream &Out,
   // FIXME: Implement the invoke/unwind instructions!
   PM.add(createLowerInvokePass());
 
-  // FIXME: Implement the switch instruction in the instruction selector!
-  if (!DisableLowerSwitch)
-    PM.add(createLowerSwitchPass());
-  
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());
 
@@ -169,10 +163,6 @@ void X86JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
   // FIXME: Implement the invoke/unwind instructions!
   PM.add(createLowerInvokePass());
 
-  // FIXME: Implement the switch instruction in the instruction selector!
-  if (!DisableLowerSwitch)
-    PM.add(createLowerSwitchPass());
-
   // Make sure that no unreachable blocks are instruction selected.
   PM.add(createUnreachableBlockEliminationPass());