SetOfInstructions &ToRemove) {
DominatorTree &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
- for (auto &Entry: ValToSExtendedUses) {
+ for (auto &Entry : ValToSExtendedUses) {
Instructions &Insts = Entry.second;
Instructions CurPts;
for (Instruction *Inst : Insts) {
DenseMap<Value *, Instruction *> SeenChains;
for (auto &BB : *Func) {
- for (auto &II: BB) {
+ for (auto &II : BB) {
Instruction *SExt = &II;
// Collect all sext operation per type.
/// print block size and offset information - debugging
void ARM64BranchRelaxation::dumpBBs() {
- for (auto &MBB: *MF) {
+ for (auto &MBB : *MF) {
const BasicBlockInfo &BBI = BlockInfo[MBB.getNumber()];
dbgs() << format("BB#%u\toffset=%08x\t", MBB.getNumber(), BBI.Offset)
<< format("size=%#x\n", BBI.Size);
ARM64FunctionInfo &ARM64FI,
const MachineDominatorTree *MDT) {
DEBUG(dbgs() << "*** Compute LOH for ADRP\n");
- for (const auto &Entry: UseToDefs) {
+ for (const auto &Entry : UseToDefs) {
unsigned Size = Entry.second.size();
if (Size == 0)
continue;
}
}
bool Found = false;
- for (auto &Use: *Users) {
+ for (auto &Use : *Users) {
if (!DefsOfPotentialCandidates.count(Use)) {
++NumTooCplxLvl1;
Found = true;
bool runOnModule(Module &M) {
DEBUG(dbgs() << getPassName() << '\n');
bool Changed = false;
- for (auto &MF: M) {
+ for (auto &MF : M) {
Changed |= runOnFunction(MF);
}
return Changed;
SmallSet<Constant *, 8> AlreadyChecked;
for (auto &MBB : F) {
- for (auto &MI: MBB) {
+ for (auto &MI : MBB) {
// Traverse the operand, looking for constant vectors
// Replace them by a load of a global variable of type constant vector
for (unsigned OpIdx = 0, EndOpIdx = MI.getNumOperands();
// precisely determine whether a store pair can be formed. But we do want to
// filter out most situations where we can't form store pairs to avoid
// computing trace metrics in those cases.
- for (auto &MBB: *MF) {
+ for (auto &MBB : *MF) {
bool SuppressSTP = false;
unsigned PrevBaseReg = 0;
- for (auto &MI: MBB) {
+ for (auto &MI : MBB) {
if (!isNarrowFPStore(MI))
continue;
unsigned BaseReg;