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Fix decoding ambiguities of stdrex and ldrex.
author
Owen Anderson
<resistor@mac.com>
Fri, 19 Nov 2010 13:11:50 +0000
(13:11 +0000)
committer
Owen Anderson
<resistor@mac.com>
Fri, 19 Nov 2010 13:11:50 +0000
(13:11 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119801
91177308
-0d34-0410-b5e6-
96231b3b80d8
lib/Target/ARM/ARMInstrThumb2.td
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diff --git
a/lib/Target/ARM/ARMInstrThumb2.td
b/lib/Target/ARM/ARMInstrThumb2.td
index ca8e7de266532633a7ea0879576c4fb86850c84b..129481d3bdd212fc144596bef74122d050bf8589 100644
(file)
--- a/
lib/Target/ARM/ARMInstrThumb2.td
+++ b/
lib/Target/ARM/ARMInstrThumb2.td
@@
-2754,10
+2754,8
@@
class T2I_ldrex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
bits<4> Rn;
bits<4> Rt;
- bits<8> imm;
let Inst{19-16} = Rn{3-0};
let Inst{15-12} = Rt{3-0};
- let Inst{7-0} = imm{7-0};
}
class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
InstrItinClass itin, string opc, string asm, string cstr,
@@
-2772,11
+2770,9
@@
class T2I_strex<bits<2> opcod, dag oops, dag iops, AddrMode am, SizeFlagVal sz,
bits<4> Rd;
bits<4> Rn;
bits<4> Rt;
- bits<8> imm;
let Inst{11-8} = Rd{3-0};
let Inst{19-16} = Rn{3-0};
let Inst{15-12} = Rt{3-0};
- let Inst{7-0} = imm{7-0};
}
let mayLoad = 1 in {