DW.EndModule();
// Emit ident information
- O << "\t.ident\t\"(llvm 1.9+) STI CBEA Cell SPU backend\"\n";
+ O << "\t.ident\t\"(llvm 2.2+) STI CBEA Cell SPU backend\"\n";
return AsmPrinter::doFinalization(M);
}
}
//===------------------------------------------------------------------===//
- //! MVT::ValueType to useful stuff structure:
+ //! MVT::ValueType to "useful stuff" mapping structure:
struct valtype_map_s {
MVT::ValueType VT;
};
const valtype_map_s valtype_map[] = {
- { MVT::i1, 0, 3, 0, 0 },
- { MVT::i8, 0, 3, 0, 0 },
- { MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ },
- { MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ },
- { MVT::i64, SPU::ORIr64, 0, 0, 0 },
- { MVT::f32, SPU::ORIf32, 0, 0, 0 },
- { MVT::f64, SPU::ORIf64, 0, 0, 0 }
+ { MVT::i1, 0, 3, 0, 0 },
+ { MVT::i8, 0, 3, 0, 0 },
+ { MVT::i16, SPU::ORHIr16, 2, SPU::BRHZ, SPU::BRHNZ },
+ { MVT::i32, SPU::ORIr32, 0, SPU::BRZ, SPU::BRNZ },
+ { MVT::i64, SPU::ORIr64, 0, 0, 0 },
+ { MVT::f32, 0, 0, 0, 0 },
+ { MVT::f64, 0, 0, 0, 0 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
unsigned VT = N->getValueType(0);
SDOperand Arg = N->getOperand(0);
SDOperand Chain = N->getOperand(1);
- SDOperand Zero = CurDAG->getTargetConstant(0, VT);
SDNode *Result;
- const valtype_map_s *vtm = getValueTypeMapEntry(VT);
-
- if (vtm->ldresult_ins == 0) {
- cerr << "LDRESULT for unsupported type: "
- << MVT::getValueTypeString(VT)
- << "\n";
- abort();
- } else
- Opc = vtm->ldresult_ins;
AddToISelQueue(Arg);
- AddToISelQueue(Zero);
- AddToISelQueue(Chain);
- Result = CurDAG->SelectNodeTo(N, Opc, VT, MVT::Other, Arg, Zero, Chain);
+ if (!MVT::isFloatingPoint(VT)) {
+ SDOperand Zero = CurDAG->getTargetConstant(0, VT);
+ const valtype_map_s *vtm = getValueTypeMapEntry(VT);
+
+ if (vtm->ldresult_ins == 0) {
+ cerr << "LDRESULT for unsupported type: "
+ << MVT::getValueTypeString(VT)
+ << "\n";
+ abort();
+ } else
+ Opc = vtm->ldresult_ins;
+
+ AddToISelQueue(Zero);
+ Result = CurDAG->SelectNodeTo(N, Opc, VT, MVT::Other, Arg, Zero, Chain);
+ } else {
+ Result =
+ CurDAG->SelectNodeTo(N, (VT == MVT::f32 ? SPU::ORf32 : SPU::ORf64),
+ MVT::Other, Arg, Arg, Chain);
+ }
+
Chain = SDOperand(Result, 1);
+ AddToISelQueue(Chain);
+
return Result;
}
setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
- setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
- setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
- setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
- setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i32, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f32, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::i64, Legal);
+ setOperationAction(ISD::BIT_CONVERT, MVT::f64, Legal);
// We cannot sextinreg(i1). Expand to shifts.
setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
LoadSDNode *LN = cast<LoadSDNode>(Op);
SDOperand basep = LN->getBasePtr();
SDOperand the_chain = LN->getChain();
+ MVT::ValueType BasepOpc = basep.Val->getOpcode();
MVT::ValueType VT = LN->getLoadedVT();
MVT::ValueType OpVT = Op.Val->getValueType(0);
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
const valtype_map_s *vtm = getValueTypeMapEntry(VT);
SDOperand Ops[8];
+ if (BasepOpc == ISD::FrameIndex) {
+ // Loading from a frame index is always properly aligned. Always.
+ return SDOperand();
+ }
+
// For an extending load of an i1 variable, just call it i8 (or whatever we
// were passed) and make it zero-extended:
if (VT == MVT::i1) {
// The vector type we really want to be when we load the 16-byte chunk
MVT::ValueType vecVT, opVecVT;
+ vecVT = MVT::v16i8;
if (VT != MVT::i1)
vecVT = MVT::getVectorType(VT, (128 / MVT::getSizeInBits(VT)));
- else
- vecVT = MVT::v16i8;
-
opVecVT = MVT::getVectorType(OpVT, (128 / MVT::getSizeInBits(OpVT)));
if (basep.getOpcode() == ISD::ADD) {
// address scheme:
SDOperand ZeroOffs = DAG.getConstant(0, PtrVT);
- SDOperand loOp = DAG.getNode(SPUISD::Lo, VT, basep, ZeroOffs);
- SDOperand hiOp = DAG.getNode(SPUISD::Hi, VT, basep, ZeroOffs);
+ SDOperand loOp = DAG.getNode(SPUISD::Lo, PtrVT, basep, ZeroOffs);
+ SDOperand hiOp = DAG.getNode(SPUISD::Hi, PtrVT, basep, ZeroOffs);
ptrp = DAG.getNode(ISD::ADD, PtrVT, loOp, hiOp);
break;
case SPU::ORIv4i32:
case SPU::ORIr32:
- case SPU::ORIf64:
- case SPU::ORIf32:
case SPU::ORIr64:
case SPU::ORHIv8i16:
case SPU::ORHIr16:
return true;
}
break;
-#if 0
- case SPU::ORIf64:
- case SPU::ORIf32:
- // Special case because there's no third immediate operand to the
- // instruction (the constant is embedded in the instruction)
- assert(MI.getOperand(0).isRegister() &&
- MI.getOperand(1).isRegister() &&
- "ORIf32/f64: operands not registers");
- sourceReg = MI.getOperand(1).getReg();
- destReg = MI.getOperand(0).getReg();
- return true;
-#endif
case SPU::ORv16i8_i8:
case SPU::ORv8i16_i16:
case SPU::ORv4i32_i32:
case SPU::ORv4i32:
case SPU::ORr32:
case SPU::ORr64:
+ case SPU::ORf32:
+ case SPU::ORf64:
case SPU::ORgprc:
assert(MI.getNumOperands() == 3 &&
MI.getOperand(0).isRegister() &&
"or\t$rT, $rA, $rB", IntegerOp,
[(set R8C:$rT, (or R8C:$rA, R8C:$rB))]>;
+// OR instruction forms that are used to copy f32 and f64 registers.
+// They do not match patterns.
+def ORf32:
+ RRForm<0b10000010000, (outs R32FP:$rT), (ins R32FP:$rA, R32FP:$rB),
+ "or\t$rT, $rA, $rB", IntegerOp,
+ [/* no pattern */]>;
+
+def ORf64:
+ RRForm<0b10000010000, (outs R64FP:$rT), (ins R64FP:$rA, R64FP:$rB),
+ "or\t$rT, $rA, $rB", IntegerOp,
+ [/* no pattern */]>;
+
// ORv*_*: Used in scalar->vector promotions:
def ORv16i8_i8:
RRForm<0b10000010000, (outs VECREG:$rT), (ins R8C:$rA, R8C:$rB),
"ori\t$rT, $rA, $val", IntegerOp,
[(set R32C:$rT, (or R32C:$rA, i32ImmUns10:$val))]>;
-// Hacked forms of or immediate to copy one 32- and 64-bit FP register
-// to another. Do not match patterns.
-def ORIf32:
- RI10Form_1<0b00100000, (outs R32FP:$rT), (ins R32FP:$rA, s10imm_i32:$val),
- "ori\t$rT, $rA, $val", IntegerOp,
- [/* no pattern */]>;
-
-def ORIf64:
- RI10Form_1<0b00100000, (outs R64FP:$rT), (ins R64FP:$rA, s10imm_i32:$val),
- "ori\t$rT, $rA, $val", IntegerOp,
- [/* no pattern */]>;
-
def ORIr64:
RI10Form_1<0b00100000, (outs R64C:$rT), (ins R64C:$rA, s10imm_i32:$val),
"ori\t$rT, $rA, $val", IntegerOp,
def SHUFB:
RRRForm<0b1000, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
"shufb\t$rT, $rA, $rB, $rC", IntegerOp,
- [/* insert intrinsic here */]>;
+ [/* no pattern */]>;
// SPUshuffle is generated in LowerVECTOR_SHUFFLE and gets replaced with SHUFB.
// See the SPUshuffle SDNode operand above, which sets up the DAG pattern
def : Pat<(SPUshuffle (v4i32 VECREG:$rA), (v4i32 VECREG:$rB), VECREG:$rC),
(SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
+def : Pat<(SPUshuffle (v4f32 VECREG:$rA), (v4f32 VECREG:$rB), VECREG:$rC),
+ (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
+
def : Pat<(SPUshuffle (v2i64 VECREG:$rA), (v2i64 VECREG:$rB), VECREG:$rC),
(SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
+def : Pat<(SPUshuffle (v2f64 VECREG:$rA), (v2f64 VECREG:$rB), VECREG:$rC),
+ (SHUFB VECREG:$rA, VECREG:$rB, VECREG:$rC)>;
+
//===----------------------------------------------------------------------===//
// Shift and rotate group:
//===----------------------------------------------------------------------===//
def : Pat<(v2f64 (bitconvert (v2f64 VECREG:$src))), (v2f64 VECREG:$src)>;
def : Pat<(f32 (bitconvert (i32 R32C:$src))), (f32 R32FP:$src)>;
+def : Pat<(f64 (bitconvert (i64 R64C:$src))), (f64 R64FP:$src)>;
//===----------------------------------------------------------------------===//
// Instruction patterns:
} else if (DestRC == SPU::R32CRegisterClass) {
BuildMI(MBB, MI, TII.get(SPU::ORIr32), DestReg).addReg(SrcReg).addImm(0);
} else if (DestRC == SPU::R32FPRegisterClass) {
- BuildMI(MBB, MI, TII.get(SPU::ORIf32), DestReg).addReg(SrcReg).addImm(0);
+ BuildMI(MBB, MI, TII.get(SPU::ORf32), DestReg).addReg(SrcReg)
+ .addReg(SrcReg);
} else if (DestRC == SPU::R64CRegisterClass) {
BuildMI(MBB, MI, TII.get(SPU::ORIr64), DestReg).addReg(SrcReg).addImm(0);
} else if (DestRC == SPU::R64FPRegisterClass) {
- BuildMI(MBB, MI, TII.get(SPU::ORIf64), DestReg).addReg(SrcReg).addImm(0);
+ BuildMI(MBB, MI, TII.get(SPU::ORf64), DestReg).addReg(SrcReg)
+ .addReg(SrcReg);
} else if (DestRC == SPU::GPRCRegisterClass) {
BuildMI(MBB, MI, TII.get(SPU::ORgprc), DestReg).addReg(SrcReg)
.addReg(SrcReg);
--- /dev/null
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep lqa %t1.s | count 13 &&
+; RUN: grep shufb %t1.s | count 13 &&
+; RUN: grep 65520 %t1.s | count 1 &&
+; RUN: grep 43981 %t1.s | count 1 &&
+; RUN: grep 13702 %t1.s | count 1 &&
+; RUN: grep 81 %t1.s | count 2 &&
+; RUN: grep 28225 %t1.s | count 1 &&
+; RUN: grep 30720 %t1.s | count 1 &&
+; RUN: grep 192 %t1.s | count 32 &&
+; RUN: grep 128 %t1.s | count 30 &&
+; RUN: grep 224 %t1.s | count 2
+
+; 1311768467750121234 => 0x 12345678 abcdef12 (4660,22136/43981,61202)
+; 18446744073709551591 => 0x ffffffff ffffffe7 (-25)
+; 18446744073708516742 => 0x ffffffff fff03586 (-1034874)
+; 5308431 => 0x 00000000 0051000F
+; 9223372038704560128 => 0x 80000000 6e417800
+
+define i64 @i64_const_1() {
+ ret i64 1311768467750121234 ;; Constant pool spill
+}
+
+define i64 @i64_const_2() {
+ ret i64 18446744073709551591 ;; IL/SHUFB
+}
+
+define i64 @i64_const_3() {
+ ret i64 18446744073708516742 ;; IHLU/IOHL/SHUFB
+}
+
+define i64 @i64_const_4() {
+ ret i64 5308431 ;; ILHU/IOHL/SHUFB
+}
+
+define i64 @i64_const_5() {
+ ret i64 511 ;; IL/SHUFB
+}
+
+define i64 @i64_const_6() {
+ ret i64 -512 ;; IL/SHUFB
+}
+
+define i64 @i64_const_7() {
+ ret i64 9223372038704560128 ;; IHLU/IOHL/SHUFB
+}
+
+define i64 @i64_const_8() {
+ ret i64 0 ;; IL
+}
+
+; 0x4005bf0a8b145769 ->
+; (ILHU 0x4005 [16389]/IOHL 0xbf0a [48906])
+; (ILHU 0x8b14 [35604]/IOHL 0x5769 [22377])
+define double @f64_const_1() {
+ ret double 0x4005bf0a8b145769 ;; ILHU/IOHL via pattern
+}
+
+define double @f64_const_2() {
+ ret double 0x0010000000000000
+}
+
+define double @f64_const_3() {
+ ret double 0x7fefffffffffffff
+}
+
+define double @f64_const_4() {
+ ret double 0x400921fb54442d18
+}
+
+define double @f64_const_5() {
+ ret double 0xbff6a09e667f3bcd ;; ILHU/IOHL via pattern
+}
+
+define double @f64_const_6() {
+ ret double 0x3ff6a09e667f3bcd
+}
+
+define double @f64_const_7() {
+ ret double 0.000000e+00
+}
--- /dev/null
+; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: llvm-as -o - %s | llc -march=cellspu -mattr=large_mem > %t2.s
+; RUN: grep il %t1.s | count 16 &&
+; RUN: grep ilhu %t1.s | count 8 &&
+; RUN: grep ilh %t1.s | count 13 &&
+; RUN: grep iohl %t1.s | count 7 &&
+; RUN: grep lqa %t1.s | count 6 &&
+; RUN: grep 24672 %t1.s | count 2 &&
+; RUN: grep 16429 %t1.s | count 1 &&
+; RUN: grep 63572 %t1.s | count 1 &&
+; RUN: grep 4660 %t1.s | count 1 &&
+; RUN: grep 22136 %t1.s | count 1 &&
+; RUN: grep 43981 %t1.s | count 1 &&
+; RUN: grep 61202 %t1.s | count 1 &&
+; RUN: grep 16393 %t1.s | count 1 &&
+; RUN: grep 8699 %t1.s | count 1 &&
+; RUN: grep 21572 %t1.s | count 1 &&
+; RUN: grep 11544 %t1.s | count 1 &&
+; RUN: grep 1311768467750121234 %t1.s | count 1 &&
+; RUN: grep lqx %t2.s | count 6 &&
+; RUN: grep ila %t2.s | count 6
+
+target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128"
+target triple = "spu-unknown-elf"
+
+; Vector constant load tests:
+
+; IL <reg>, 2
+define <4 x i32> @v4i32_constvec() {
+ ret <4 x i32> < i32 2, i32 2, i32 2, i32 2 >
+}
+
+; Spill to constant pool
+define <4 x i32> @v4i32_constpool() {
+ ret <4 x i32> < i32 2, i32 1, i32 1, i32 2 >
+}
+
+; Max negative range for IL
+define <4 x i32> @v4i32_constvec_2() {
+ ret <4 x i32> < i32 -32768, i32 -32768, i32 -32768, i32 -32768 >
+}
+
+; ILHU <reg>, 73 (0x49)
+; 4784128 = 0x490000
+define <4 x i32> @v4i32_constvec_3() {
+ ret <4 x i32> < i32 4784128, i32 4784128,
+ i32 4784128, i32 4784128 >
+}
+
+; ILHU <reg>, 61 (0x3d)
+; IOHL <reg>, 15395 (0x3c23)
+define <4 x i32> @v4i32_constvec_4() {
+ ret <4 x i32> < i32 4013091, i32 4013091,
+ i32 4013091, i32 4013091 >
+}
+
+; ILHU <reg>, 0x5050 (20560)
+; IOHL <reg>, 0x5050 (20560)
+; Tests for whether we expand the size of the bit pattern properly, because
+; this could be interpreted as an i8 pattern (0x50)
+define <4 x i32> @v4i32_constvec_5() {
+ ret <4 x i32> < i32 1347440720, i32 1347440720,
+ i32 1347440720, i32 1347440720 >
+}
+
+; ILH
+define <8 x i16> @v8i16_constvec_1() {
+ ret <8 x i16> < i16 32767, i16 32767, i16 32767, i16 32767,
+ i16 32767, i16 32767, i16 32767, i16 32767 >
+}
+
+; ILH
+define <8 x i16> @v8i16_constvec_2() {
+ ret <8 x i16> < i16 511, i16 511, i16 511, i16 511, i16 511,
+ i16 511, i16 511, i16 511 >
+}
+
+; ILH
+define <8 x i16> @v8i16_constvec_3() {
+ ret <8 x i16> < i16 -512, i16 -512, i16 -512, i16 -512, i16 -512,
+ i16 -512, i16 -512, i16 -512 >
+}
+
+; ILH <reg>, 24672 (0x6060)
+; Tests whether we expand the size of the bit pattern properly, because
+; this could be interpreted as an i8 pattern (0x60)
+define <8 x i16> @v8i16_constvec_4() {
+ ret <8 x i16> < i16 24672, i16 24672, i16 24672, i16 24672, i16 24672,
+ i16 24672, i16 24672, i16 24672 >
+}
+
+; ILH <reg>, 24672 (0x6060)
+; Tests whether we expand the size of the bit pattern properly, because
+; this is an i8 pattern but has to be expanded out to i16 to load it
+; properly into the vector register.
+define <16 x i8> @v16i8_constvec_1() {
+ ret <16 x i8> < i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96,
+ i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96, i8 96 >
+}
+
+define <4 x float> @v4f32_constvec_1() {
+entry:
+ ret <4 x float> < float 0x4005BF0A80000000,
+ float 0x4005BF0A80000000,
+ float 0x4005BF0A80000000,
+ float 0x4005BF0A80000000 >
+}
+
+define <4 x float> @v4f32_constvec_2() {
+entry:
+ ret <4 x float> < float 0.000000e+00,
+ float 0.000000e+00,
+ float 0.000000e+00,
+ float 0.000000e+00 >
+}
+
+
+define <4 x float> @v4f32_constvec_3() {
+entry:
+ ret <4 x float> < float 0x4005BF0A80000000,
+ float 0x3810000000000000,
+ float 0x47EFFFFFE0000000,
+ float 0x400921FB60000000 >
+}
+
+; 1311768467750121234 => 0x 12345678 abcdef12
+; HI32_hi: 4660
+; HI32_lo: 22136
+; LO32_hi: 43981
+; LO32_lo: 61202
+define <2 x i64> @i64_constvec_1() {
+entry:
+ ret <2 x i64> < i64 1311768467750121234,
+ i64 1311768467750121234 >
+}
+
+define <2 x i64> @i64_constvec_2() {
+entry:
+ ret <2 x i64> < i64 1, i64 1311768467750121234 >
+}
+
+define <2 x double> @f64_constvec_1() {
+entry:
+ ret <2 x double> < double 0x400921fb54442d18,
+ double 0xbff6a09e667f3bcd >
+}
+
+; 0x400921fb 54442d18 ->
+; (ILHU 0x4009 [16393]/IOHL 0x21fb [ 8699])
+; (ILHU 0x5444 [21572]/IOHL 0x2d18 [11544])
+define <2 x double> @f64_constvec_2() {
+entry:
+ ret <2 x double> < double 0x400921fb54442d18,
+ double 0x400921fb54442d18 >
+}
projects / oota-llvm.git / commitdiff