we can't do this directly in lowering, so we need this case

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24951 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index c135f314e08299768d90ef4ca5715ff24b93134c..177365081fd124e27ae672c63ef8bf4d2083327d 100644 (file)
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -343,6 +343,14 @@ SDOperand IA64DAGToDAGISel::Select(SDOperand Op) {
 
   case ISD::Register: return Op; // XXX: this is a hack, tblgen one day?
   
+  case IA64ISD::GETFD: {
+    SDOperand Input = Select(N->getOperand(0));
+    SDOperand Result = CurDAG->getTargetNode(IA64::GETFD, MVT::i64, MVT::Flag, Input);
+    CodeGenMap[Op.getValue(0)] = Result;
+    CodeGenMap[Op.getValue(1)] = Result.getValue(1);
+    return Result.getValue(Op.ResNo);
+  } 
+  
   case ISD::CALL:
   case ISD::TAILCALL: { {
         // FIXME: This is a workaround for a bug in tblgen.