Be less specific about register allocation ordering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134308 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/test/CodeGen/X86/atomic-or.ll b/test/CodeGen/X86/atomic-or.ll
index 9db6f6f06dd6a2311282fb37c7de279653914dc9..164252de3c15fae5a6fc610470068a54532076cc 100644 (file)
--- a/test/CodeGen/X86/atomic-or.ll
+++ b/test/CodeGen/X86/atomic-or.ll
@@ -11,7 +11,7 @@ entry:
 ; CHECK: t1:
 ; CHECK: movl    $2147483648, %eax
 ; CHECK: lock
-; CHECK-NEXT: orq %rax, (%rdi)
+; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
   %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483648)
   call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
   ret void
@@ -26,7 +26,7 @@ entry:
 ; CHECK: t2:
 ; CHECK-NOT: movl
 ; CHECK: lock
-; CHECK-NEXT: orq $2147483644, (%rdi)
+; CHECK-NEXT: orq $2147483644, (%r{{.*}})
   %0 = call i64 @llvm.atomic.load.or.i64.p0i64(i64* %tmp, i64 2147483644)
   call void @llvm.memory.barrier(i1 true, i1 true, i1 true, i1 true, i1 true)
   ret void