[SelectionDAG] Scalar shift amounts may require legalization

The shift amount may be too small to cope with promoted left hand side,
make sure to promote it as well.

This fixes PR23664.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@238503 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index eeaebf780cc34cb3e73cc400d9678abedee54124..278929dff224e1500db5f790a9c845812ce6d5f0 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -604,7 +604,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
   SDValue Res = GetPromotedInteger(N->getOperand(0));
   SDValue Amt = N->getOperand(1);
 SDValue DAGTypeLegalizer::PromoteIntRes_SHL(SDNode *N) {
   SDValue Res = GetPromotedInteger(N->getOperand(0));
   SDValue Amt = N->getOperand(1);

-  Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
+  if (!TLI.isTypeLegal(Amt.getValueType()))
+    Amt = ZExtPromotedInteger(N->getOperand(1));

   return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
 }
 
   return DAG.getNode(ISD::SHL, SDLoc(N), Res.getValueType(), Res, Amt);
 }
 


@@ -628,7 +629,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRA(SDNode *N) {
   // The input value must be properly sign extended.
   SDValue Res = SExtPromotedInteger(N->getOperand(0));
   SDValue Amt = N->getOperand(1);
   // The input value must be properly sign extended.
   SDValue Res = SExtPromotedInteger(N->getOperand(0));
   SDValue Amt = N->getOperand(1);

-  Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
+  if (!TLI.isTypeLegal(Amt.getValueType()))
+    Amt = ZExtPromotedInteger(N->getOperand(1));

   return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
 }
 
   return DAG.getNode(ISD::SRA, SDLoc(N), Res.getValueType(), Res, Amt);
 }
 


@@ -636,7 +638,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
   // The input value must be properly zero extended.
   SDValue Res = ZExtPromotedInteger(N->getOperand(0));
   SDValue Amt = N->getOperand(1);
   // The input value must be properly zero extended.
   SDValue Res = ZExtPromotedInteger(N->getOperand(0));
   SDValue Amt = N->getOperand(1);

-  Amt = Amt.getValueType().isVector() ? ZExtPromotedInteger(Amt) : Amt;
+  if (!TLI.isTypeLegal(Amt.getValueType()))
+    Amt = ZExtPromotedInteger(N->getOperand(1));

   return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
 }
 
   return DAG.getNode(ISD::SRL, SDLoc(N), Res.getValueType(), Res, Amt);
 }