Add support for 64-bit set-on-less-than instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141695 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td
index 0bdc371e0fe6567bb3116e4896f9a9e7c6aa071a..d95557a1a495a5a7fc24858e4f056d62905186d6 100644 (file)
--- a/lib/Target/Mips/Mips64InstrInfo.td
+++ b/lib/Target/Mips/Mips64InstrInfo.td
@@ -131,12 +131,16 @@ class CountLeading64<bits<6> func, string instr_asm, list<dag> pattern>:
 /// Arithmetic Instructions (ALU Immediate)
 def DADDiu   : ArithI64<0x19, "daddiu", add, simm16_64, immSExt16>;
 def DANDi    : LogicI64<0x0c, "andi", and>;
+def SLTi64   : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>;
+def SLTiu64  : SetCC_I<0x0b, "sltiu", setult, simm16_64, immSExt16, CPU64Regs>;
 def DORi     : LogicI64<0x0d, "ori",  or>;
 def DXORi    : LogicI64<0x0e, "xori",  xor>;
 
 /// Arithmetic Instructions (3-Operand, R-Type)
 def DADDu    : ArithR64<0x00, 0x2d, "daddu", add, IIAlu, 1>;
 def DSUBu    : ArithR64<0x00, 0x2f, "dsubu", sub, IIAlu>;
+def SLT64    : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>;
+def SLTu64   : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
 def DAND     : LogicR64<0x24, "and", and>;
 def DOR      : LogicR64<0x25, "or", or>;
 def DXOR     : LogicR64<0x26, "xor", xor>;
@@ -232,3 +236,29 @@ def : Pat<(zextloadi32_u addr:$a), (DSRL (DSLL (ULW64 addr:$a), 32), 32)>,
 
 // hi/lo relocs
 def : Pat<(i64 (MipsLo tglobaladdr:$in)), (DADDiu ZERO_64, tglobaladdr:$in)>;
+
+// setcc patterns
+def : Pat<(seteq CPU64Regs:$lhs, CPU64Regs:$rhs),
+          (SLTu64 (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
+def : Pat<(setne CPU64Regs:$lhs, CPU64Regs:$rhs),
+          (SLTu64 ZERO_64, (DXOR CPU64Regs:$lhs, CPU64Regs:$rhs))>;
+
+def : Pat<(setle CPU64Regs:$lhs, CPU64Regs:$rhs),
+          (XORi (SLT64 CPU64Regs:$rhs, CPU64Regs:$lhs), 1)>;
+def : Pat<(setule CPU64Regs:$lhs, CPU64Regs:$rhs),
+          (XORi (SLTu64 CPU64Regs:$rhs, CPU64Regs:$lhs), 1)>;
+
+def : Pat<(setgt CPU64Regs:$lhs, CPU64Regs:$rhs),
+          (SLT64 CPU64Regs:$rhs, CPU64Regs:$lhs)>;
+def : Pat<(setugt CPU64Regs:$lhs, CPU64Regs:$rhs),
+          (SLTu64 CPU64Regs:$rhs, CPU64Regs:$lhs)>;
+
+def : Pat<(setge CPU64Regs:$lhs, CPU64Regs:$rhs),
+          (XORi (SLT64 CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
+def : Pat<(setuge CPU64Regs:$lhs, CPU64Regs:$rhs),
+          (XORi (SLTu64 CPU64Regs:$lhs, CPU64Regs:$rhs), 1)>;
+
+def : Pat<(setge CPU64Regs:$lhs, immSExt16:$rhs),
+          (XORi (SLTi64 CPU64Regs:$lhs, immSExt16:$rhs), 1)>;
+def : Pat<(setuge CPU64Regs:$lhs, immSExt16:$rhs),
+          (XORi (SLTiu64 CPU64Regs:$lhs, immSExt16:$rhs), 1)>;

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 46b8a281e7725861e523c00b61490a5403b9b340..432199c5cea7305c124d484bbca0a602cbdf8842 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -406,18 +406,18 @@ class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
 }
 
 // SetCC
-class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
-      PatFrag cond_op>:
-  FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
-     !strconcat(instr_asm, "\t$dst, $b, $c"),
-     [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
+class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
+              RegisterClass RC>:
+  FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
+     !strconcat(instr_asm, "\t$rd, $rs, $rt"),
+     [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
      IIAlu>;
 
-class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
-      Operand Od, PatLeaf imm_type>:
-  FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
-     !strconcat(instr_asm, "\t$dst, $b, $c"),
-     [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
+class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
+              PatLeaf imm_type, RegisterClass RC>:
+  FI<op, (outs CPURegs:$rd), (ins RC:$rs, Od:$i),
+     !strconcat(instr_asm, "\t$rd, $rs, $i"),
+     [(set CPURegs:$rd, (cond_op RC:$rs, imm_type:$i))],
      IIAlu>;
 
 // Unconditional branch
@@ -615,8 +615,8 @@ let usesCustomInserter = 1 in {
 /// Arithmetic Instructions (ALU Immediate)
 def ADDiu   : ArithI<0x09, "addiu", add, simm16, immSExt16>;
 def ADDi    : ArithOverflowI<0x08, "addi",  add, simm16, immSExt16>;
-def SLTi    : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
-def SLTiu   : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
+def SLTi    : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
+def SLTiu   : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
 def ANDi    : LogicI<0x0c, "andi", and>;
 def ORi     : LogicI<0x0d, "ori",  or>;
 def XORi    : LogicI<0x0e, "xori",  xor>;
@@ -627,8 +627,8 @@ def ADDu    : ArithR<0x00, 0x21, "addu", add, IIAlu, 1>;
 def SUBu    : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
 def ADD     : ArithOverflowR<0x00, 0x20, "add", 1>;
 def SUB     : ArithOverflowR<0x00, 0x22, "sub">;
-def SLT     : SetCC_R<0x00, 0x2a, "slt", setlt>;
-def SLTu    : SetCC_R<0x00, 0x2b, "sltu", setult>;
+def SLT     : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
+def SLTu    : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
 def AND     : LogicR<0x24, "and", and>;
 def OR      : LogicR<0x25, "or",  or>;
 def XOR     : LogicR<0x26, "xor", xor>;