return VReg;
}
+SDOperand X86TargetLowering::LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
+ const CCValAssign &VA,
+ MachineFrameInfo *MFI,
+ SDOperand Root, unsigned i) {
+ // Create the nodes corresponding to a load from this parameter slot.
+ int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
+ VA.getLocMemOffset());
+ SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
+
+ unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
+
+ if (Flags & ISD::ParamFlags::ByVal)
+ return FIN;
+ else
+ return DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0);
+}
+
SDOperand X86TargetLowering::LowerCCCArguments(SDOperand Op, SelectionDAG &DAG,
bool isStdCall) {
unsigned NumArgs = Op.Val->getNumValues() - 1;
ArgValues.push_back(ArgValue);
} else {
assert(VA.isMemLoc());
-
- // Create the nodes corresponding to a load from this parameter slot.
- int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
- VA.getLocMemOffset());
- SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
- ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
+ ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, Root, i));
}
}
ArgValues.push_back(ArgValue);
} else {
assert(VA.isMemLoc());
-
- // Create the nodes corresponding to a load from this parameter slot.
- int FI = MFI->CreateFixedObject(MVT::getSizeInBits(VA.getValVT())/8,
- VA.getLocMemOffset());
- SDOperand FIN = DAG.getFrameIndex(FI, getPointerTy());
-
- unsigned Flags = cast<ConstantSDNode>(Op.getOperand(3 + i))->getValue();
- if (Flags & ISD::ParamFlags::ByVal)
- ArgValues.push_back(FIN);
- else
- ArgValues.push_back(DAG.getLoad(VA.getValVT(), Root, FIN, NULL, 0));
+ ArgValues.push_back(LowerMemArgument(Op, DAG, VA, MFI, Root, i));
}
}
unsigned CallingConv, SelectionDAG &DAG);
+ SDOperand LowerMemArgument(SDOperand Op, SelectionDAG &DAG,
+ const CCValAssign &VA, MachineFrameInfo *MFI,
+ SDOperand Root, unsigned i);
+
SDOperand LowerMemOpCallTo(SDOperand Op, SelectionDAG &DAG,
const SDOperand &StackPtr,
const CCValAssign &VA, SDOperand Chain,
-; RUN: llvm-as < %s | llc -march=x86-64 | grep movq.*8.*rsp.*rax
+; RUN: llvm-as < %s | llc -march=x86-64 | grep {movq 8(%rsp), %rax}
+; RUN: llvm-as < %s | llc -march=x86 > %t
+; RUN: grep {movl 8(%esp), %edx} %t
+; RUN: grep {movl 4(%esp), %eax} %t
%struct.s = type { i64, i64, i64 }