Support for microMIPS load effective address.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198010 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MicroMipsInstrInfo.td b/lib/Target/Mips/MicroMipsInstrInfo.td
index 4f068dfe15c86ff244b7a93d9996640a1c1dcec9..84cba5fb20e7cbd9d01863dae44dc01bde4e7b1c 100644 (file)
--- a/lib/Target/Mips/MicroMipsInstrInfo.td
+++ b/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -78,6 +78,9 @@ let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
                  ADDI_FM_MM<0x1c>;
   def LUi_MM   : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM;
 
+  def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>,
+                     LW_FM_MM<0xc>;
+
   /// Arithmetic Instructions (3-Operand, R-Type)
   def ADDu_MM  : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>;
   def SUBu_MM  : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>;

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index 809ef11fd388ace93e6bb13c3ef624c2e9b38f37..65e2b7a6a05f1169510ab64f560a3847f095a1b5 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -747,7 +747,8 @@ class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
 
 class EffectiveAddress<string opstr, RegisterOperand RO> :
   InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
-         [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
+         [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
+         !strconcat(opstr, "_lea")> {
   let isCodeGenOnly = 1;
   let DecoderMethod = "DecodeMem";
 }
@@ -1094,7 +1095,7 @@ def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
 // instructions. The same not happens for stack address copies, so an
 // add op with mem ComplexPattern is used and the stack address copy
 // can be matched. It's similar to Sparc LEA_ADDRi
-def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
+def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
 
 // MADD*/MSUB*
 def MADD  : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;

diff --git a/test/MC/Mips/micromips-load-effective-address.s b/test/MC/Mips/micromips-load-effective-address.s
new file mode 100644 (file)
index 0000000..afba760
--- /dev/null
+++ b/test/MC/Mips/micromips-load-effective-address.s
@@ -0,0 +1,29 @@
+; RUN: llc %s -march=mipsel -mattr=micromips -filetype=asm \
+; RUN: -relocation-model=pic -O3 -o - | FileCheck %s
+
+define i32 @sum(i32* %x, i32* %y) nounwind uwtable {
+entry:
+  %x.addr = alloca i32*, align 8
+  %y.addr = alloca i32*, align 8
+  store i32* %x, i32** %x.addr, align 8
+  store i32* %y, i32** %y.addr, align 8
+  %0 = load i32** %x.addr, align 8
+  %1 = load i32* %0, align 4
+  %2 = load i32** %y.addr, align 8
+  %3 = load i32* %2, align 4
+  %add = add nsw i32 %1, %3
+  ret i32 %add
+}
+
+define i32 @main() nounwind uwtable {
+entry:
+  %retval = alloca i32, align 4
+  %x = alloca i32, align 4
+  %y = alloca i32, align 4
+  store i32 0, i32* %retval
+  %call = call i32 @sum(i32* %x, i32* %y)
+  ret i32 %call
+}
+
+; CHECK: addiu ${{[0-9]+}}, $sp, {{[0-9]+}}
+; CHECK: addiu ${{[0-9]+}}, $sp, {{[0-9]+}}