}
};
-}
-
extern void StartPassTimer(llvm::Pass *);
extern void StopPassTimer(llvm::Pass *);
+}
+
#endif
return Result;
}
-void dumpToDOUT(SparseBitVector<> *bitmap) {
+static void dumpToDOUT(SparseBitVector<> *bitmap) {
#ifndef NDEBUG
raw_os_ostream OS(*DOUT);
dump(*bitmap, OS);
// indices from Idxs that should be left out when inserting into the resulting
// struct. To is the result struct built so far, new insertvalue instructions
// build on that.
-Value *BuildSubAggregate(Value *From, Value* To, const Type *IndexedType,
- SmallVector<unsigned, 10> &Idxs,
- unsigned IdxSkip,
- LLVMContext &Context,
- Instruction *InsertBefore) {
+static Value *BuildSubAggregate(Value *From, Value* To, const Type *IndexedType,
+ SmallVector<unsigned, 10> &Idxs,
+ unsigned IdxSkip,
+ LLVMContext &Context,
+ Instruction *InsertBefore) {
const llvm::StructType *STy = llvm::dyn_cast<llvm::StructType>(IndexedType);
if (STy) {
// Save the original To argument so we can modify it
// insertvalue instruction somewhere).
//
// All inserted insertvalue instructions are inserted before InsertBefore
-Value *BuildSubAggregate(Value *From, const unsigned *idx_begin,
- const unsigned *idx_end, LLVMContext &Context,
- Instruction *InsertBefore) {
+static Value *BuildSubAggregate(Value *From, const unsigned *idx_begin,
+ const unsigned *idx_end, LLVMContext &Context,
+ Instruction *InsertBefore) {
assert(InsertBefore && "Must have someplace to insert!");
const Type *IndexedType = ExtractValueInst::getIndexedType(From->getType(),
idx_begin,
clEnumValEnd),
cl::init(local));
-cl::opt<bool>
+static cl::opt<bool>
ScheduleSpills("schedule-spills",
cl::desc("Schedule spill code"),
cl::init(false));
VirtRegRewriter::~VirtRegRewriter() {}
+namespace {
/// This class is intended for use with the new spilling framework only. It
/// rewrites vreg def/uses to use the assigned preg, but does not insert any
};
+}
+
// ************************************************************************ //
+namespace {
+
/// AvailableSpills - As the local rewriter is scanning and rewriting an MBB
/// from top down, keep track of which spill slots or remat are available in
/// each register.
std::vector<MachineOperand*> &KillOps);
};
+}
+
// ************************************************************************ //
// Given a location where a reload of a spilled register or a remat of
return NewInsertLoc;
}
-
+
+namespace {
+
// ReusedOp - For each reused operand, we keep track of a bit of information,
// in case we need to rollback upon processing a new operand. See comments
// below.
}
};
+}
// ****************** //
// Utility Functions //
// Local Spiller Implementation //
// ***************************** //
+namespace {
+
class VISIBILITY_HIDDEN LocalRewriter : public VirtRegRewriter {
MachineRegisterInfo *RegInfo;
const TargetRegisterInfo *TRI;
};
+}
+
llvm::VirtRegRewriter* llvm::createVirtRegRewriter() {
switch (RewriterOpt) {
default: llvm_unreachable("Unreachable!");
* linking with libc_nonshared.a and -Wl,--export-dynamic doesn't make 'stat'
* available as an exported symbol, so we have to add it explicitly.
*/
+namespace {
class StatSymbols {
public:
StatSymbols() {
sys::DynamicLibrary::AddSymbol("mknod", (void*)(intptr_t)mknod);
}
};
+}
static StatSymbols initStatSymbols;
#endif // __linux__
return 0;
}
-void Sleep(unsigned n) {
+void sys::Sleep(unsigned n) {
::sleep(n);
}
char Thumb2ITBlockPass::ID = 0;
}
-ARMCC::CondCodes getPredicate(const MachineInstr *MI,
- const Thumb2InstrInfo *TII) {
+static ARMCC::CondCodes getPredicate(const MachineInstr *MI,
+ const Thumb2InstrInfo *TII) {
unsigned Opc = MI->getOpcode();
if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
return ARMCC::AL;
}
//! Generate the address of a constant pool entry.
-SDValue
+static SDValue
LowerConstantPool(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
MVT PtrVT = Op.getValueType();
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
}
//! Lower a BUILD_VECTOR instruction creatively:
-SDValue
+static SDValue
LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
MVT EltVT = VT.getVectorElementType();
}
}
+namespace {
+
class TargetLoweringObjectFileSparc : public TargetLoweringObjectFileELF {
public:
void getSectionFlagsAsString(SectionKind Kind,
}
};
+}
SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
: TargetLowering(TM, new TargetLoweringObjectFileSparc()) {
}
/// StripSymbolNames - Strip symbol names.
-bool StripSymbolNames(Module &M, bool PreserveDbgInfo) {
+static bool StripSymbolNames(Module &M, bool PreserveDbgInfo) {
SmallPtrSet<const GlobalValue*, 8> llvmUsedValues;
findUsedValues(M.getGlobalVariable("llvm.used"), llvmUsedValues);
// StripDebugInfo - Strip debug info in the module if it exists.
// To do this, we remove llvm.dbg.func.start, llvm.dbg.stoppoint, and
// llvm.dbg.region.end calls, and any globals they point to if now dead.
-bool StripDebugInfo(Module &M) {
+static bool StripDebugInfo(Module &M) {
SmallPtrSet<const GlobalValue*, 8> llvmUsedValues;
findUsedValues(M.getGlobalVariable("llvm.used"), llvmUsedValues);
}
}
+namespace {
/// StoreIndexSearchPredicate - This is a helper predicate used to search by the
/// first element of a pair.
}
};
+}
+
/// PromoteSingleBlockAlloca - Many allocas are only used within a single basic
/// block. If this is the case, avoid traversing the CFG and inserting a lot of
/// potentially useless PHI nodes by just performing a single linear pass over
}
/// If TimingInfo is enabled then start pass timer.
-void StartPassTimer(Pass *P) {
+void llvm::StartPassTimer(Pass *P) {
if (TheTimeInfo)
TheTimeInfo->passStarted(P);
}
/// If TimingInfo is enabled then stop pass timer.
-void StopPassTimer(Pass *P) {
+void llvm::StopPassTimer(Pass *P) {
if (TheTimeInfo)
TheTimeInfo->passEnded(P);
}