ARM assembly parsing and encoding for SMC instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135782 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 7b675c8532752899234dbe47dcd8cc186a956ede..fb822355cd68999a3619e662d50623bb47a489d5 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1742,8 +1742,8 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
 
 
 // Secure Monitor Call is a system instruction -- for disassembly only
-def SMC : ABI<0b0001, (outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
-              [/* For disassembly only; pattern left blank */]> {
+def SMC : ABI<0b0001, (outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
+              []> {
   bits<4> opt;
   let Inst{23-4} = 0b01100000000000000111;
   let Inst{3-0} = opt;

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 6241b31da60b3c7ac54c6779d97318b14f84e8d1..287c2d94d282a26b881c3bda43d896318063f7ec 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -3170,7 +3170,7 @@ def t2DBG : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "dbg", "\t$opt", []> {
 
 // Secure Monitor Call is a system instruction -- for disassembly only
 // Option = Inst{19-16}
-def t2SMC : T2I<(outs), (ins i32imm:$opt), NoItinerary, "smc", "\t$opt",
+def t2SMC : T2I<(outs), (ins imm0_15:$opt), NoItinerary, "smc", "\t$opt",
                 [/* For disassembly only; pattern left blank */]> {
   let Inst{31-27} = 0b11110;
   let Inst{26-20} = 0b1111111;

diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s
index 42a60a463fa98c065b1ebc2da281a76aa7f68110..dcaf602780bc1a01130dfde58ff81cd6c966ed2c 100644 (file)
--- a/test/MC/ARM/basic-arm-instructions.s
+++ b/test/MC/ARM/basic-arm-instructions.s
@@ -1359,6 +1359,15 @@ _func:
 @ CHECK: shsub8        r4, r8, r2              @ encoding: [0xf2,0x4f,0x38,0xe6]
 @ CHECK: shsub8gt      r4, r8, r2      @ encoding: [0xf2,0x4f,0x38,0xc6]
 
+@------------------------------------------------------------------------------
+@ SMC
+@------------------------------------------------------------------------------
+        smc #0xf
+        smceq #0
+
+@ CHECK: smc   #15                     @ encoding: [0x7f,0x00,0x60,0xe1]
+@ CHECK: smceq #0                      @ encoding: [0x70,0x00,0x60,0x01]
+
 
 @------------------------------------------------------------------------------
 @ STM*