Remove bunch of gcc 4.3-related warnings from Target

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMCodeEmitter.cpp b/lib/Target/ARM/ARMCodeEmitter.cpp
index 62ea102ad5d6aeec9d1329554a569126005af80a..f4ee6b0f64997dc5cc98859de7408c004ad9033b 100644 (file)
--- a/lib/Target/ARM/ARMCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMCodeEmitter.cpp
@@ -475,8 +475,8 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
         }
       }
       // set the field related to shift operations (except rrx).
-      if(ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx)
-        if(IsShiftByRegister) {
+      if (ARM_AM::getSORegShOp(MO2.getImm()) != ARM_AM::rrx) {
+        if (IsShiftByRegister) {
           // set the value of bit[11:8] (register Rs).
           assert(TargetRegisterInfo::isPhysicalRegister(MO1.getReg()));
           op = ARMRegisterInfo::getRegisterNumbering(MO1.getReg());
@@ -487,6 +487,7 @@ unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
           op = ARM_AM::getSORegOffset(MO2.getImm());
           Value |= op << 7;
         }
+      }
       break;
     }
     default: assert(false && "Unknown operand type!");

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index d1538f32c8e5224963b16a290c91d756bb1ffb67..92ab18d5775a9218a888d42b4df35eb265519b9a 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -1551,7 +1551,7 @@ static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
     if ((V & (Scale - 1)) != 0)
       return false;
     V /= Scale;
-    return V == V & ((1LL << 5) - 1);
+    return V == (V & ((1LL << 5) - 1));
   }
 
   if (V < 0)
@@ -1562,10 +1562,10 @@ static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
   case MVT::i8:
   case MVT::i32:
     // +- imm12
-    return V == V & ((1LL << 12) - 1);
+    return V == (V & ((1LL << 12) - 1));
   case MVT::i16:
     // +- imm8
-    return V == V & ((1LL << 8) - 1);
+    return V == (V & ((1LL << 8) - 1));
   case MVT::f32:
   case MVT::f64:
     if (!Subtarget->hasVFP2())
@@ -1573,7 +1573,7 @@ static bool isLegalAddressImmediate(int64_t V, MVT::ValueType VT,
     if ((V & 3) != 0)
       return false;
     V >>= 2;
-    return V == V & ((1LL << 8) - 1);
+    return V == (V & ((1LL << 8) - 1));
   }
 }
 

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index dccc77f7f61887dd24eb3f6a5074ff0b728a9afe..3be0d7a8f4d616ae791b741391f04d9b4357ed09 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -1328,7 +1328,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
         if (AFI->getGPRCalleeSavedArea2Size() ||
             AFI->getDPRCalleeSavedAreaSize()  ||
             AFI->getDPRCalleeSavedAreaOffset()||
-            hasFP(MF))
+            hasFP(MF)) {
           if (NumBytes)
             BuildMI(MBB, MBBI, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
               .addImm(NumBytes)
@@ -1336,6 +1336,7 @@ void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
           else
             BuildMI(MBB, MBBI, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
               .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
+        }
       } else if (NumBytes) {
         emitSPUpdate(MBB, MBBI, NumBytes, ARMCC::AL, 0, false, TII, *this);
       }

diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index c9a87dc01096f396bceb99996abb43cdf52f74e3..9a33d0b8e4cab0de54ab40ba86308bb7d55ceeef 100644 (file)
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -272,8 +272,8 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF,
                                      MachineBasicBlock &MBB) const {
   const MachineFrameInfo *MFI = MF.getFrameInfo();
   MachineBasicBlock::iterator MBBI = prior(MBB.end());
-  assert(MBBI->getOpcode() == Alpha::RETDAG ||
-         MBBI->getOpcode() == Alpha::RETDAGp
+  assert((MBBI->getOpcode() == Alpha::RETDAG ||
+          MBBI->getOpcode() == Alpha::RETDAGp)
          && "Can only insert epilog into returning blocks");
 
   bool FP = hasFP(MF);

diff --git a/lib/Target/CBackend/CBackend.cpp b/lib/Target/CBackend/CBackend.cpp
index d01c2ab74afa4f6dfc8610159c8fb7d6b848a444..305c8de3740bdfa21b0d03a88594d489fb537e20 100644 (file)
--- a/lib/Target/CBackend/CBackend.cpp
+++ b/lib/Target/CBackend/CBackend.cpp
@@ -2912,7 +2912,7 @@ void CWriter::printIndexingExpression(Value *Ptr, gep_type_iterator I,
     HasImplicitAddress = false;  // HIA is only true if we haven't addressed yet
   }
 
-  assert(!HasImplicitAddress || (CI && CI->isNullValue()) &&
+  assert((!HasImplicitAddress || (CI && CI->isNullValue())) &&
          "Can only have implicit address with direct accessing");
 
   if (HasImplicitAddress) {

diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h
index 510f7712328600d0354878bbba8ae81b3889d435..0666115ea7665c313a6cb1ebd81184f2744cac0e 100644 (file)
--- a/lib/Target/IA64/IA64RegisterInfo.h
+++ b/lib/Target/IA64/IA64RegisterInfo.h
@@ -17,8 +17,6 @@
 #include "llvm/Target/TargetRegisterInfo.h"
 #include "IA64GenRegisterInfo.h.inc"
 
-namespace llvm { class llvm::Type; }
-
 namespace llvm {
 
 class TargetInstrInfo;

diff --git a/lib/Target/MSIL/MSILWriter.cpp b/lib/Target/MSIL/MSILWriter.cpp
index 72ccc3a2c394ec37606e717a40d126f36d6aa5e8..be9fc64bd8e0e6ffce600821a059f02e9837c270 100644 (file)
--- a/lib/Target/MSIL/MSILWriter.cpp
+++ b/lib/Target/MSIL/MSILWriter.cpp
@@ -202,7 +202,7 @@ void MSILWriter::printModuleStartup() {
   }
 
   bool RetVoid = (F->getReturnType()->getTypeID() == Type::VoidTyID);
-  if (BadSig || !F->getReturnType()->isInteger() && !RetVoid) {
+  if (BadSig || (!F->getReturnType()->isInteger() && !RetVoid)) {
     Out << "\tldc.i4.0\n";
   } else {
     Out << "\tcall\t" << getTypeName(F->getReturnType()) <<

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index f4aaaadd18476cfb055ee2296ff1cd185509614f..888881c7d30d114dcfc34e98c5b9de596f20fb9a 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -935,7 +935,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
       bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
       if (LD->getValueType(0) != MVT::i64) {
         // Handle PPC32 integer and normal FP loads.
-        assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+        assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
         switch (LoadedVT) {
           default: assert(0 && "Invalid PPC load type!");
           case MVT::f64: Opcode = PPC::LFDU; break;
@@ -947,7 +947,7 @@ SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
         }
       } else {
         assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
-        assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
+        assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
         switch (LoadedVT) {
           default: assert(0 && "Invalid PPC load type!");
           case MVT::i64: Opcode = PPC::LDU; break;

diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index 1ab0bcfb67afa09bd16c4a55ee72197ca0c829cc..f770eeb54eccabb097982437cd4c975830b8edbd 100644 (file)
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -92,11 +92,12 @@ PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS,
     FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
     InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
 
-  if (getRelocationModel() == Reloc::Default)
+  if (getRelocationModel() == Reloc::Default) {
     if (Subtarget.isDarwin())
       setRelocationModel(Reloc::DynamicNoPIC);
     else
       setRelocationModel(Reloc::Static);
+  }
 }
 
 /// Override this for PowerPC.  Tail merging happily breaks up instruction issue

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 61a4d7a511695c3515da8ba7abc1a2088992b07a..b5e91ce71449493715d5d7caf5233989439d379d 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -1029,12 +1029,13 @@ bool X86TargetLowering::IsCalleePop(SDOperand Op) {
 CCAssignFn *X86TargetLowering::CCAssignFnForNode(SDOperand Op) const {
   unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
   
-  if (Subtarget->is64Bit())
+  if (Subtarget->is64Bit()) {
     if (CC == CallingConv::Fast && PerformTailCallOpt)
       return CC_X86_64_TailCall;
     else
       return CC_X86_64_C;
-  
+  }
+
   if (CC == CallingConv::X86_FastCall)
     return CC_X86_32_FastCall;
   else if (CC == CallingConv::Fast && PerformTailCallOpt)
@@ -3358,11 +3359,12 @@ SDOperand RewriteAsNarrowerShuffle(SDOperand V1, SDOperand V2,
   default: assert(false && "Unexpected!");
   }
 
-  if (NewWidth == 2)
+  if (NewWidth == 2) {
     if (MVT::isInteger(VT))
       NewVT = MVT::v2i64;
     else
       NewVT = MVT::v2f64;
+  }
   unsigned Scale = NumElems / NewWidth;
   SmallVector<SDOperand, 8> MaskVec;
   for (unsigned i = 0; i < NumElems; i += Scale) {

diff --git a/lib/Target/X86/X86IntelAsmPrinter.cpp b/lib/Target/X86/X86IntelAsmPrinter.cpp
index 804790d45b86da9fd098a8ae48fd84f8f2beb5b2..64013fcff5690c12b357fc9a3523a9770f4737ce 100644 (file)
--- a/lib/Target/X86/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/X86IntelAsmPrinter.cpp
@@ -221,13 +221,14 @@ void X86IntelAsmPrinter::printMemReference(const MachineInstr *MI, unsigned Op,
   } else {
     int DispVal = DispSpec.getImm();
     if (DispVal || (!BaseReg.getReg() && !IndexReg.getReg())) {
-      if (NeedPlus)
+      if (NeedPlus) {
         if (DispVal > 0)
           O << " + ";
         else {
           O << " - ";
           DispVal = -DispVal;
         }
+      }
       O << DispVal;
     }
   }

diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp
index fb46cfc6ac02388c700e1e94e5a5f90a6b1af674..019b65c6deb2d70acfd1ccb96b4ff5dc79434410 100644 (file)
--- a/lib/Target/X86/X86Subtarget.cpp
+++ b/lib/Target/X86/X86Subtarget.cpp
@@ -36,7 +36,7 @@ bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
                                        bool isDirectCall) const
 {
   // FIXME: PIC
-  if (TM.getRelocationModel() != Reloc::Static)
+  if (TM.getRelocationModel() != Reloc::Static) {
     if (isTargetDarwin()) {
       return (!isDirectCall &&
               (GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
@@ -48,6 +48,7 @@ bool X86Subtarget::GVRequiresExtraLoad(const GlobalValue* GV,
     } else if (isTargetCygMing() || isTargetWindows()) {
       return (GV->hasDLLImportLinkage());
     }
+  }
   
   return false;
 }

diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 3c527c50b620981694c58218c0489c03272e4046..850eb386fb5b81805c9368e1fb7aed629d822c41 100644 (file)
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -119,11 +119,12 @@ X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
               Subtarget.getStackAlignment(), Subtarget.is64Bit() ? -8 : -4),
     InstrInfo(*this), JITInfo(*this), TLInfo(*this) {
   DefRelocModel = getRelocationModel();
-  if (getRelocationModel() == Reloc::Default)
+  if (getRelocationModel() == Reloc::Default) {
     if (Subtarget.isTargetDarwin() || Subtarget.isTargetCygMing())
       setRelocationModel(Reloc::DynamicNoPIC);
     else
       setRelocationModel(Reloc::Static);
+  }
   if (Subtarget.is64Bit()) {
     // No DynamicNoPIC support under X86-64.
     if (getRelocationModel() == Reloc::DynamicNoPIC)
@@ -135,16 +136,17 @@ X86TargetMachine::X86TargetMachine(const Module &M, const std::string &FS,
 
   if (Subtarget.isTargetCygMing())
     Subtarget.setPICStyle(PICStyle::WinPIC);
-  else if (Subtarget.isTargetDarwin())
+  else if (Subtarget.isTargetDarwin()) {
     if (Subtarget.is64Bit())
       Subtarget.setPICStyle(PICStyle::RIPRel);
     else
       Subtarget.setPICStyle(PICStyle::Stub);
-  else if (Subtarget.isTargetELF())
+  } else if (Subtarget.isTargetELF()) {
     if (Subtarget.is64Bit())
       Subtarget.setPICStyle(PICStyle::RIPRel);
     else
       Subtarget.setPICStyle(PICStyle::GOT);
+  }
 }
 
 //===----------------------------------------------------------------------===//