Make FMA4 imply AVX so that YMM registers would be available. Necessitates removing...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147369 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index d053c76de78d8f50a73e9eb996f9074e6621cb19..66779361da169ca8234f7c97c812953e259c6ab8 100644 (file)
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -77,7 +77,8 @@ def FeatureFastUAMem : SubtargetFeature<"fast-unaligned-mem",
                                         "IsUAMemFast", "true",
                                         "Fast unaligned memory access">;
 def FeatureSSE4A   : SubtargetFeature<"sse4a", "HasSSE4A", "true",
-                                      "Support SSE 4a instructions">;
+                                      "Support SSE 4a instructions",
+                                      [FeatureSSE3]>;
 
 def FeatureAVX     : SubtargetFeature<"avx", "HasAVX", "true",
                                       "Enable AVX instructions">;
@@ -90,8 +91,9 @@ def FeatureFMA3    : SubtargetFeature<"fma3", "HasFMA3", "true",
                                       "Enable three-operand fused multiple-add",
                                       [FeatureAVX]>;
 def FeatureFMA4    : SubtargetFeature<"fma4", "HasFMA4", "true",
-                                      "Enable four-operand fused multiple-add">;
-def FeatureXOP    : SubtargetFeature<"xop", "HasXOP", "true",
+                                      "Enable four-operand fused multiple-add",
+                                      [FeatureAVX]>;
+def FeatureXOP     : SubtargetFeature<"xop", "HasXOP", "true",
                                       "Enable XOP instructions">;
 def FeatureVectorUAMem : SubtargetFeature<"vector-unaligned-mem",
                                           "HasVectorUAMem", "true",
@@ -201,12 +203,12 @@ def : Proc<"athlon64-sse3",   [FeatureSSE3,   Feature3DNowA, FeatureCMPXCHG16B,
 def : Proc<"amdfam10",        [FeatureSSE3,   FeatureSSE4A,
                                Feature3DNowA, FeatureCMPXCHG16B, FeatureLZCNT,
                                FeaturePOPCNT, FeatureSlowBTMem]>;
-// FIXME: Disabling AVX for now since it's not ready.
+// FIXME: Disabling AVX/FMA4 for now since it's not ready.
 def : Proc<"bdver1",          [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
-                               FeatureAES, FeatureCLMUL, FeatureFMA4,
+                               FeatureAES, FeatureCLMUL,
                                FeatureXOP, FeatureLZCNT, FeaturePOPCNT]>;
 def : Proc<"bdver2",          [FeatureSSE42, FeatureSSE4A, FeatureCMPXCHG16B,
-                               FeatureAES, FeatureCLMUL, FeatureFMA4,
+                               FeatureAES, FeatureCLMUL,
                                FeatureXOP, FeatureF16C, FeatureLZCNT,
                                FeaturePOPCNT, FeatureBMI]>;