/*ctor*/
-MachineInstrInfo::MachineInstrInfo(const MachineInstrDescriptor* _desc,
+MachineInstrInfo::MachineInstrInfo(const TargetMachine& tgt,
+ const MachineInstrDescriptor* _desc,
unsigned int _descSize,
unsigned int _numRealOpCodes)
- : desc(_desc), descSize(_descSize), numRealOpCodes(_numRealOpCodes)
+ : target(tgt),
+ desc(_desc), descSize(_descSize), numRealOpCodes(_numRealOpCodes)
{
// FIXME: TargetInstrDescriptors should not be global
assert(TargetInstrDescriptors == NULL && desc != NULL);
// Interface to machine description for instruction scheduling
//---------------------------------------------------------------------------
-MachineSchedInfo::MachineSchedInfo(int NumSchedClasses,
- const MachineInstrInfo* Mii,
+MachineSchedInfo::MachineSchedInfo(const TargetMachine& tgt,
+ int NumSchedClasses,
const InstrClassRUsage* ClassRUsages,
const InstrRUsageDelta* UsageDeltas,
const InstrIssueDelta* IssueDeltas,
unsigned int NumUsageDeltas,
unsigned int NumIssueDeltas)
- : numSchedClasses(NumSchedClasses), mii(Mii),
+ : target(tgt),
+ numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()),
classRUsages(ClassRUsages), usageDeltas(UsageDeltas),
issueDeltas(IssueDeltas), numUsageDeltas(NumUsageDeltas),
numIssueDeltas(NumIssueDeltas)