Add more patterns to match in the integer comparison test harnesses.

Fix bugs encountered, mostly due to range matching for immediates;
the CellSPU's 10-bit immediates are sign extended, covering a
larger range of unsigned values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48575 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 1d4b28b4c5332b2160485a9254b56a0d51a60c1e..b81f277d55f3ad6ef90b8121d8863c572add858b 100644 (file)
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -65,14 +65,14 @@ namespace {
   bool
   isI32IntU10Immediate(ConstantSDNode *CN)
   {
-    return isU10Constant((int) CN->getValue());
+    return isU10Constant(CN->getSignExtended());
   }
 
   //! ConstantSDNode predicate for i16 sign-extended, 10-bit immediate values
   bool
   isI16IntS10Immediate(ConstantSDNode *CN)
   {
-    return isS10Constant((short) CN->getValue());
+    return isS10Constant(CN->getSignExtended());
   }
 
   //! SDNode predicate for i16 sign-extended, 10-bit immediate values

diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index bd288d3bd6a039a04ba5b75372bcdeb06b7a6473..03efdc8c4be01345a959cfbdc7e536a522d450ee 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -2708,7 +2708,7 @@ multiclass CmpGtrByteImm
                                                v16i8SExt8Imm:$val))]>;
   def r8:
     CGTBIInst<(outs R8C:$rT), (ins R8C:$rA, s10imm_i8:$val),
-             [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
+              [(set R8C:$rT, (setgt R8C:$rA, immSExt8:$val))]>;
 }
 
 class CGTHInst<dag OOL, dag IOL, list<dag> pattern> :
@@ -2962,14 +2962,14 @@ def : SETCCBinOpImm<setult, R16C, i16ImmSExt10, i16, NORr16,
                     CLGTHIr16, CEQHIr16>;
 def : Pat<(setule R16C:$rA, R16C:$rB),
           (XORHIr16 (CLGTHr16 R16C:$rA, R16C:$rB), 0xffff)>;
-def :  Pat<(setule R16C:$rA, i16ImmUns10:$imm),
+def :  Pat<(setule R16C:$rA, i16ImmSExt10:$imm),
            (XORHIr16 (CLGTHIr16 R16C:$rA, i16ImmSExt10:$imm), 0xffff)>;
 
 def : SETCCBinOpReg<setuge, R32C, ORr32, CLGTr32, CEQr32>;
-def : SETCCBinOpImm<setuge, R32C, i32ImmUns10, i32,
+def : SETCCBinOpImm<setuge, R32C, i32ImmSExt10, i32,
                     ORr32, CLGTIr32, CEQIr32>;
 def : SETCCBinOpReg<setult, R32C, NORr32, CLGTr32, CEQr32>;
-def : SETCCBinOpImm<setult, R32C, immSExt8, i32, NORr32, CLGTIr32, CEQIr32>;
+def : SETCCBinOpImm<setult, R32C, i32ImmSExt10, i32, NORr32, CLGTIr32, CEQIr32>;
 def : Pat<(setule R32C:$rA, R32C:$rB),
           (XORIr32 (CLGTr32 R32C:$rA, R32C:$rB), 0xffffffff)>;
 def : Pat<(setule R32C:$rA, i32ImmSExt10:$imm),

diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td
index da4b0f2efcefad871a99f0c71dd07c3fe15bf18b..1e8eff56525e8a7e1b8662ad023f8916f2b90f62 100644 (file)
--- a/lib/Target/CellSPU/SPUOperands.td
+++ b/lib/Target/CellSPU/SPUOperands.td
@@ -76,9 +76,8 @@ def uimm7: PatLeaf<(imm), [{
 // immSExt8 predicate - True if the immediate fits in an 8-bit sign extended
 // field.
 def immSExt8  : PatLeaf<(imm), [{
-  int Value = (int) N->getValue();
-  int Value8 = (Value << 24) >> 24;
-  return (Value < 0xff && (Value8 >= -128 && Value8 < 127));
+  int Value = int(N->getSignExtended());
+  return (Value >= -(1 << 8) && Value <= (1 << 8) - 1);
 }]>;
 
 // immU8: immediate, unsigned 8-bit quantity

diff --git a/test/CodeGen/CellSPU/icmp16.ll b/test/CodeGen/CellSPU/icmp16.ll
index 4dc0ad89a4ef0aeffc07248239f7d434c83e8103..bace03105411f506eb6e96504311bb7e6b4733f3 100644 (file)
--- a/test/CodeGen/CellSPU/icmp16.ll
+++ b/test/CodeGen/CellSPU/icmp16.ll
@@ -1,4 +1,14 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep ilh                                %t1.s | count 5
+; RUN: grep ceqh                               %t1.s | count 29
+; RUN: grep ceqhi                              %t1.s | count 13
+; RUN: grep clgth                              %t1.s | count 15
+; RUN: grep cgth                               %t1.s | count 14
+; RUN: grep cgthi                              %t1.s | count 6
+; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 17
+; RUN: grep {selb\t\\\$3, \\\$4, \\\$5, \\\$3} %t1.s | count 6
 
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
@@ -113,14 +123,14 @@ entry:
 
 define i16 @icmp_ugt_immed01_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
 entry:
-       %A = icmp ugt i16 %arg1, 511
+       %A = icmp ugt i16 %arg1, 500
        %B = select i1 %A, i16 %val1, i16 %val2
        ret i16 %B
 }
 
 define i16 @icmp_ugt_immed02_i16(i16 %arg1, i16 %val1, i16 %val2) nounwind {
 entry:
-       %A = icmp ugt i16 %arg1, 65534
+       %A = icmp ugt i16 %arg1, 0
        %B = select i1 %A, i16 %val1, i16 %val2
        ret i16 %B
 }

diff --git a/test/CodeGen/CellSPU/icmp32.ll b/test/CodeGen/CellSPU/icmp32.ll
index 0a7f1f5c3060412e47cd1ca1aa00e55c0f032d27..4f74b0dd04290acad4138fc7ba86cb9cc4b8ef22 100644 (file)
--- a/test/CodeGen/CellSPU/icmp32.ll
+++ b/test/CodeGen/CellSPU/icmp32.ll
@@ -1,9 +1,9 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
 ; RUN: grep ila                                %t1.s | count 6
 ; RUN: grep ceq                                %t1.s | count 28
-; RUN: grep ceqi                               %t1.s | count 11
+; RUN: grep ceqi                               %t1.s | count 12
 ; RUN: grep clgt                               %t1.s | count 16
-; RUN: grep clgti                              %t1.s | count 5
+; RUN: grep clgti                              %t1.s | count 6
 ; RUN: grep cgt                                %t1.s | count 16
 ; RUN: grep cgti                               %t1.s | count 6
 ; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7

diff --git a/test/CodeGen/CellSPU/icmp8.ll b/test/CodeGen/CellSPU/icmp8.ll
index fd556d0113129940f325c290230b509e8cf4a4ef..d246481f03a1911fe7a21bb14fb0310c93d5e40d 100644 (file)
--- a/test/CodeGen/CellSPU/icmp8.ll
+++ b/test/CodeGen/CellSPU/icmp8.ll
@@ -1,4 +1,13 @@
 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
+; RUN: grep ceqb                               %t1.s | count 24
+; RUN: grep ceqbi                              %t1.s | count 12
+; RUN: grep clgtb                              %t1.s | count 11
+; RUN: grep cgtb                               %t1.s | count 13
+; RUN: grep cgtbi                              %t1.s | count 5
+; RUN: grep {selb\t\\\$3, \\\$6, \\\$5, \\\$3} %t1.s | count 7
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$6, \\\$3} %t1.s | count 3
+; RUN: grep {selb\t\\\$3, \\\$5, \\\$4, \\\$3} %t1.s | count 11
+; RUN: grep {selb\t\\\$3, \\\$4, \\\$5, \\\$3} %t1.s | count 4
 
 target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
 target triple = "spu"
@@ -184,7 +193,7 @@ entry:
 
 define i8 @icmp_sgt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
 entry:
-       %A = icmp sgt i8 %arg1, 127
+       %A = icmp sgt i8 %arg1, 96
        %B = select i1 %A, i8 %val1, i8 %val2
        ret i8 %B
 }
@@ -237,14 +246,14 @@ entry:
 
 define i8 @icmp_slt_immed01_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
 entry:
-       %A = icmp slt i8 %arg1, 127
+       %A = icmp slt i8 %arg1, 96
        %B = select i1 %A, i8 %val1, i8 %val2
        ret i8 %B
 }
 
 define i8 @icmp_slt_immed02_i8(i8 %arg1, i8 %val1, i8 %val2) nounwind {
 entry:
-       %A = icmp slt i8 %arg1, -128
+       %A = icmp slt i8 %arg1, -120
        %B = select i1 %A, i8 %val1, i8 %val2
        ret i8 %B
 }