#include "llvm/Target/TargetRegistry.h"
using namespace llvm;
+static cl::opt<bool>
+LdStBeforeSched("ldstopti-before-sched2", cl::Hidden,
+ cl::desc("Move ld / st multiple pass before postalloc scheduling"));
+
static const MCAsmInfo *createMCAsmInfo(const Target &T,
const StringRef &TT) {
Triple TheTriple(TT);
return true;
}
+bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
+ // FIXME: temporarily disabling load / store optimization pass for Thumb1.
+ if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only())
+ if (LdStBeforeSched)
+ PM.add(createARMLoadStoreOptimizationPass());
+
+ return true;
+}
+
bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM,
CodeGenOpt::Level OptLevel) {
// FIXME: temporarily disabling load / store optimization pass for Thumb1.
if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) {
- PM.add(createARMLoadStoreOptimizationPass());
+ if (!LdStBeforeSched)
+ PM.add(createARMLoadStoreOptimizationPass());
PM.add(createIfConverterPass());
}
// Pass Pipeline Configuration
virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
+ virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
MachineCodeEmitter &MCE);