When there is a 2-instruction spill sequence, record
authorDale Johannesen <dalej@apple.com>
Thu, 29 Oct 2009 01:15:40 +0000 (01:15 +0000)
committerDale Johannesen <dalej@apple.com>
Thu, 29 Oct 2009 01:15:40 +0000 (01:15 +0000)
the second (store) instruction in SpillSlotToUsesMap
consistently.  I don't think this matters functionally,
but it's cleaner and Evan wants it this way.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85463 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/VirtRegRewriter.cpp

index a9ff1ad9aeddff0f4d19aed531b992d4876e5ace..fd80f460992b6a6fa868329dbe41e6ffe641788e 100644 (file)
@@ -1432,7 +1432,7 @@ private:
 
     MachineBasicBlock::iterator oldNextMII = next(MII);
     TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
-    MachineInstr *StoreMI = next(MII);
+    MachineInstr *StoreMI = prior(oldNextMII);
     VRM.addSpillSlotUse(StackSlot, StoreMI);
     DEBUG(errs() << "Store:\t" << *StoreMI);
 
@@ -1751,8 +1751,9 @@ private:
           const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
           unsigned Phys = VRM.getPhys(VirtReg);
           int StackSlot = VRM.getStackSlot(VirtReg);
+          MachineBasicBlock::iterator oldNextMII = next(MII);
           TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
-          MachineInstr *StoreMI = next(MII);
+          MachineInstr *StoreMI = prior(oldNextMII);
           VRM.addSpillSlotUse(StackSlot, StoreMI);
           DEBUG(errs() << "Store:\t" << *StoreMI);
           VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);