Remove trailing whitespac

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186032 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 98806551e4d70b9e25cb28a43e00270b0fb97203..02fdb3fd88364f86081424f47f650614d93187a1 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -6151,7 +6151,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
       if (N10 == N0 && isNegatibleForFree(N11, LegalOperations, TLI,
                                           &DAG.getTarget().Options))
         return GetNegatedExpression(N11, DAG, LegalOperations);
-      
+
       if (N11 == N0 && isNegatibleForFree(N10, LegalOperations, TLI,
                                           &DAG.getTarget().Options))
         return GetNegatedExpression(N10, DAG, LegalOperations);
@@ -6172,7 +6172,7 @@ SDValue DAGCombiner::visitFSUB(SDNode *N) {
 
     // fold (fsub x, (fmul y, z)) -> (fma (fneg y), z, x)
     // Note: Commutes FSUB operands.
-    if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse()) 
+    if (N1.getOpcode() == ISD::FMUL && N1->hasOneUse())
       return DAG.getNode(ISD::FMA, dl, VT,
                          DAG.getNode(ISD::FNEG, dl, VT,
                          N1.getOperand(0)),