Parser.Lex(); // Eat left bracket token.
const AsmToken &BaseRegTok = Parser.getTok();
+ SMLoc BaseRegLoc = BaseRegTok.getLoc();
if (BaseRegTok.isNot(AsmToken::Identifier))
- return Error(BaseRegTok.getLoc(), "register expected");
+ return Error(BaseRegLoc, "register expected");
int64_t Reg = tryParseRegister();
if (Reg == -1)
- return Error(BaseRegTok.getLoc(), "register expected");
+ return Error(BaseRegLoc, "register expected");
+
+ if (!ARM64MCRegisterClasses[ARM64::GPR64spRegClassID].contains(Reg))
+ return Error(BaseRegLoc, "invalid operand for instruction");
// If there is an offset expression, parse it.
const MCExpr *OffsetExpr = nullptr;
// diagnose.
MatchResult = Match_InvalidMemoryIndexed;
}
+ else if(Operands.size() == 3 && Operands.size() == ErrorInfo + 1 &&
+ ((ARM64Operand *)Operands[ErrorInfo])->isImm()) {
+ MatchResult = Match_InvalidLabel;
+ }
SMLoc ErrorLoc = ((ARM64Operand *)Operands[ErrorInfo])->getStartLoc();
if (ErrorLoc == SMLoc())
ErrorLoc = IDLoc;
case Match_InvalidMovImm32Shift:
case Match_InvalidMovImm64Shift:
case Match_InvalidFPImm:
+ case Match_InvalidMemoryIndexed:
case Match_InvalidMemoryIndexed8:
case Match_InvalidMemoryIndexed16:
case Match_InvalidMemoryIndexed32SImm7:
; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
; CHECK-ERRORS: ldr x0, [x0, #804]!
; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
+; CHECK-ERRORS: error: invalid operand for instruction
; CHECK-ERRORS: ldr w0, [w0, #301]!
-; CHECK-ERRORS: ^
+; CHECK-ERRORS: ^
; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
; CHECK-ERRORS: ldr x0, [x0], #804
; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
+; CHECK-ERRORS: error: invalid operand for instruction
; CHECK-ERRORS: ldr w0, [w0], #301
-; CHECK-ERRORS: ^
+; CHECK-ERRORS: ^
; CHECK-ERRORS: error: index must be a multiple of 4 in range [-256, 252].
; CHECK-ERRORS: ldp w3, w4, [x5, #11]!
; CHECK-ERRORS: ^