Make MachineInstr::getDesc return a reference instead
of a pointer, since it can never be null.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45695
91177308-0d34-0410-b5e6-
96231b3b80d8
42 files changed:
-class TargetInstrDescriptor;
template <typename T> struct ilist_traits;
template <typename T> struct ilist;
template <typename T> struct ilist_traits;
template <typename T> struct ilist;
/// MachineInstr - Representation of each machine instruction.
///
class MachineInstr {
/// MachineInstr - Representation of each machine instruction.
///
class MachineInstr {
- const TargetInstrDescriptor *TID; // Instruction descriptor.
+ const TargetInstrDesc *TID; // Instruction descriptor.
unsigned short NumImplicitOps; // Number of implicit operands (which
// are determined at construction time).
unsigned short NumImplicitOps; // Number of implicit operands (which
// are determined at construction time).
/// MachineInstr ctor - This constructor create a MachineInstr and add the
/// implicit operands. It reserves space for number of operands specified by
/// MachineInstr ctor - This constructor create a MachineInstr and add the
/// implicit operands. It reserves space for number of operands specified by
- /// TargetInstrDescriptor.
- explicit MachineInstr(const TargetInstrDescriptor &TID, bool NoImp = false);
+ /// TargetInstrDesc.
+ explicit MachineInstr(const TargetInstrDesc &TID, bool NoImp = false);
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
/// the MachineInstr is created and added to the end of the specified basic
/// block.
///
/// MachineInstr ctor - Work exactly the same as the ctor above, except that
/// the MachineInstr is created and added to the end of the specified basic
/// block.
///
- MachineInstr(MachineBasicBlock *MBB, const TargetInstrDescriptor &TID);
+ MachineInstr(MachineBasicBlock *MBB, const TargetInstrDesc &TID);
/// getDesc - Returns the target instruction descriptor of this
/// MachineInstr.
/// getDesc - Returns the target instruction descriptor of this
/// MachineInstr.
- const TargetInstrDescriptor *getDesc() const { return TID; }
+ const TargetInstrDesc &getDesc() const { return *TID; }
/// getOpcode - Returns the opcode of this MachineInstr.
///
/// getOpcode - Returns the opcode of this MachineInstr.
///
/// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
/// the current instruction with a new one.
///
/// setInstrDescriptor - Replace the instruction descriptor (thus opcode) of
/// the current instruction with a new one.
///
- void setInstrDescriptor(const TargetInstrDescriptor &tid) { TID = &tid; }
+ void setInstrDescriptor(const TargetInstrDesc &tid) { TID = &tid; }
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with.
/// RemoveOperand - Erase an operand from an instruction, leaving it with one
/// fewer operand than it started with.
-class TargetInstrDescriptor;
class MachineInstrBuilder {
MachineInstr *MI;
class MachineInstrBuilder {
MachineInstr *MI;
/// BuildMI - Builder interface. Specify how to create the initial instruction
/// itself.
///
/// BuildMI - Builder interface. Specify how to create the initial instruction
/// itself.
///
-inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID) {
+inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID) {
return MachineInstrBuilder(new MachineInstr(TID));
}
/// BuildMI - This version of the builder sets up the first operand as a
/// destination virtual register.
///
return MachineInstrBuilder(new MachineInstr(TID));
}
/// BuildMI - This version of the builder sets up the first operand as a
/// destination virtual register.
///
-inline MachineInstrBuilder BuildMI(const TargetInstrDescriptor &TID,
+inline MachineInstrBuilder BuildMI(const TargetInstrDesc &TID,
unsigned DestReg) {
return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
}
unsigned DestReg) {
return MachineInstrBuilder(new MachineInstr(TID)).addReg(DestReg, true);
}
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
- const TargetInstrDescriptor &TID,
+ const TargetInstrDesc &TID,
unsigned DestReg) {
MachineInstr *MI = new MachineInstr(TID);
BB.insert(I, MI);
unsigned DestReg) {
MachineInstr *MI = new MachineInstr(TID);
BB.insert(I, MI);
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
- const TargetInstrDescriptor &TID) {
+ const TargetInstrDesc &TID) {
MachineInstr *MI = new MachineInstr(TID);
BB.insert(I, MI);
return MachineInstrBuilder(MI);
MachineInstr *MI = new MachineInstr(TID);
BB.insert(I, MI);
return MachineInstrBuilder(MI);
/// destination register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
/// destination register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
- const TargetInstrDescriptor &TID) {
+ const TargetInstrDesc &TID) {
return BuildMI(*BB, BB->end(), TID);
}
return BuildMI(*BB, BB->end(), TID);
}
/// operand as a destination virtual register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
/// operand as a destination virtual register.
///
inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB,
- const TargetInstrDescriptor &TID,
+ const TargetInstrDesc &TID,
unsigned DestReg) {
return BuildMI(*BB, BB->end(), TID, DestReg);
}
unsigned DestReg) {
return BuildMI(*BB, BB->end(), TID, DestReg);
}
class SelectionDAG;
class SelectionDAGISel;
class TargetInstrInfo;
class SelectionDAG;
class SelectionDAGISel;
class TargetInstrInfo;
- class TargetInstrDescriptor;
class TargetMachine;
class TargetRegisterClass;
class TargetMachine;
class TargetRegisterClass;
DenseMap<SDOperand, unsigned> &VRBaseMap);
void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
DenseMap<SDOperand, unsigned> &VRBaseMap);
void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
- const TargetInstrDescriptor &II,
+ const TargetInstrDesc &II,
DenseMap<SDOperand, unsigned> &VRBaseMap);
void EmitSchedule();
DenseMap<SDOperand, unsigned> &VRBaseMap);
void EmitSchedule();
DenseMap<SDOperand, unsigned> &VRBaseMap);
void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
DenseMap<SDOperand, unsigned> &VRBaseMap);
void AddOperand(MachineInstr *MI, SDOperand Op, unsigned IIOpNum,
- const TargetInstrDescriptor *II,
+ const TargetInstrDesc *II,
DenseMap<SDOperand, unsigned> &VRBaseMap);
};
DenseMap<SDOperand, unsigned> &VRBaseMap);
};
// Machine Instruction Flags and Description
//===----------------------------------------------------------------------===//
// Machine Instruction Flags and Description
//===----------------------------------------------------------------------===//
-/// TargetInstrDescriptor flags - These should be considered private to the
-/// implementation of the TargetInstrDescriptor class. Clients should use the
-/// predicate methods on TargetInstrDescriptor, not use these directly. These
-/// all correspond to bitfields in the TargetInstrDescriptor::Flags field.
+/// TargetInstrDesc flags - These should be considered private to the
+/// implementation of the TargetInstrDesc class. Clients should use the
+/// predicate methods on TargetInstrDesc, not use these directly. These
+/// all correspond to bitfields in the TargetInstrDesc::Flags field.
namespace TID {
enum {
Variadic = 0,
namespace TID {
enum {
Variadic = 0,
-/// TargetInstrDescriptor - Describe properties that are true of each
+/// TargetInstrDesc - Describe properties that are true of each
/// instruction in the target description file. This captures information about
/// side effects, register use and many other things. There is one instance of
/// this struct for each target instruction class, and the MachineInstr class
/// points to this struct directly to describe itself.
/// instruction in the target description file. This captures information about
/// side effects, register use and many other things. There is one instance of
/// this struct for each target instruction class, and the MachineInstr class
/// points to this struct directly to describe itself.
-class TargetInstrDescriptor {
public:
unsigned short Opcode; // The opcode number.
unsigned short NumOperands; // Num of args (may be more if variable_ops)
public:
unsigned short Opcode; // The opcode number.
unsigned short NumOperands; // Num of args (may be more if variable_ops)
/// dest operand. Returns -1 if there isn't one.
int findTiedToSrcOperand(unsigned OpNum) const;
/// dest operand. Returns -1 if there isn't one.
int findTiedToSrcOperand(unsigned OpNum) const;
+ /// getOpcode - Return the opcode number for this descriptor.
+ unsigned getOpcode() const {
+ return Opcode;
+ }
+
/// getName - Return the name of the record in the .td file for this
/// instruction, for example "ADD8ri".
const char *getName() const {
/// getName - Return the name of the record in the .td file for this
/// instruction, for example "ADD8ri".
const char *getName() const {
/// TargetInstrInfo - Interface to description of machine instructions
///
class TargetInstrInfo {
/// TargetInstrInfo - Interface to description of machine instructions
///
class TargetInstrInfo {
- const TargetInstrDescriptor* desc; // raw array to allow static init'n
- unsigned NumOpcodes; // number of entries in the desc array
- unsigned numRealOpCodes; // number of non-dummy op codes
+ const TargetInstrDesc *Descriptors; // Raw array to allow static init'n
+ unsigned NumOpcodes; // Number of entries in the desc array
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
TargetInstrInfo(const TargetInstrInfo &); // DO NOT IMPLEMENT
void operator=(const TargetInstrInfo &); // DO NOT IMPLEMENT
public:
- TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned NumOpcodes);
+ TargetInstrInfo(const TargetInstrDesc *desc, unsigned NumOpcodes);
virtual ~TargetInstrInfo();
// Invariant opcodes: All instruction sets have these as their low opcodes.
virtual ~TargetInstrInfo();
// Invariant opcodes: All instruction sets have these as their low opcodes.
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
/// get - Return the machine instruction descriptor that corresponds to the
/// specified instruction opcode.
///
- const TargetInstrDescriptor& get(unsigned Opcode) const {
- assert(Opcode < NumOpcodes);
- return desc[Opcode];
+ const TargetInstrDesc &get(unsigned Opcode) const {
+ assert(Opcode < NumOpcodes && "Invalid opcode!");
+ return Descriptors[Opcode];
}
/// isTriviallyReMaterializable - Return true if the instruction is trivially
/// rematerializable, meaning it has no side effects and requires no operands
/// that aren't always available.
bool isTriviallyReMaterializable(MachineInstr *MI) const {
}
/// isTriviallyReMaterializable - Return true if the instruction is trivially
/// rematerializable, meaning it has no side effects and requires no operands
/// that aren't always available.
bool isTriviallyReMaterializable(MachineInstr *MI) const {
- return MI->getDesc()->isRematerializable() &&
+ return MI->getDesc().isRematerializable() &&
isReallyTriviallyReMaterializable(MI);
}
isReallyTriviallyReMaterializable(MI);
}
/// effects that are not captured by any operands of the instruction or other
/// flags.
bool hasUnmodelledSideEffects(MachineInstr *MI) const {
/// effects that are not captured by any operands of the instruction or other
/// flags.
bool hasUnmodelledSideEffects(MachineInstr *MI) const {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (TID->hasNoSideEffects()) return false;
- if (!TID->hasConditionalSideEffects()) return true;
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (TID.hasNoSideEffects()) return false;
+ if (!TID.hasConditionalSideEffects()) return true;
return !isReallySideEffectFree(MI); // May have side effects
}
protected:
return !isReallySideEffectFree(MI); // May have side effects
}
protected:
/// libcodegen, not in libtarget.
class TargetInstrInfoImpl : public TargetInstrInfo {
protected:
/// libcodegen, not in libtarget.
class TargetInstrInfoImpl : public TargetInstrInfo {
protected:
- TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
+ TargetInstrInfoImpl(const TargetInstrDesc *desc, unsigned NumOpcodes)
: TargetInstrInfo(desc, NumOpcodes) {}
public:
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
: TargetInstrInfo(desc, NumOpcodes) {}
public:
virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
class TargetData;
class TargetSubtarget;
class TargetInstrInfo;
class TargetData;
class TargetSubtarget;
class TargetInstrInfo;
-class TargetInstrDescriptor;
class TargetJITInfo;
class TargetLowering;
class TargetFrameInfo;
class TargetJITInfo;
class TargetLowering;
class TargetFrameInfo;
MachineBasicBlock::iterator E) {
unsigned Time = 0;
for (; I != E; ++I) {
MachineBasicBlock::iterator E) {
unsigned Time = 0;
for (; I != E; ++I) {
- const TargetInstrDescriptor *TID = I->getDesc();
- if (TID->isCall())
+ const TargetInstrDesc &TID = I->getDesc();
+ if (TID.isCall())
- else if (TID->isSimpleLoad() || TID->mayStore())
+ else if (TID.isSimpleLoad() || TID.mayStore())
MachineInstr *MBB1I = --MBB1->end();
MachineInstr *MBB2I = --MBB2->end();
MachineInstr *MBB1I = --MBB1->end();
MachineInstr *MBB2I = --MBB2->end();
- return MBB2I->getDesc()->isCall() && !MBB1I->getDesc()->isCall();
+ return MBB2I->getDesc().isCall() && !MBB1I->getDesc().isCall();
}
/// OptimizeBlock - Analyze and optimize control flow related to the specified
}
/// OptimizeBlock - Analyze and optimize control flow related to the specified
// If this branch is the only thing in its block, see if we can forward
// other blocks across it.
if (CurTBB && CurCond.empty() && CurFBB == 0 &&
// If this branch is the only thing in its block, see if we can forward
// other blocks across it.
if (CurTBB && CurCond.empty() && CurFBB == 0 &&
- MBB->begin()->getDesc()->isBranch() && CurTBB != MBB) {
+ MBB->begin()->getDesc().isBranch() && CurTBB != MBB) {
// This block may contain just an unconditional branch. Because there can
// be 'non-branch terminators' in the block, try removing the branch and
// then seeing if the block is empty.
// This block may contain just an unconditional branch. Because there can
// be 'non-branch terminators' in the block, try removing the branch and
// then seeing if the block is empty.
BBE = MF.end(); BBI != BBE; ++BBI)
for (MachineBasicBlock::iterator MI = BBI->begin(),
ME = BBI->end(); MI != ME; ++MI)
BBE = MF.end(); BBI != BBE; ++BBI)
for (MachineBasicBlock::iterator MI = BBI->begin(),
ME = BBI->end(); MI != ME; ++MI)
- if (MI->getDesc()->isCall())
+ if (MI->getDesc().isCall())
for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
MI != E; ++MI) {
if (MI->getOpcode() != TargetInstrInfo::LABEL) {
for (MachineBasicBlock::const_iterator MI = I->begin(), E = I->end();
MI != E; ++MI) {
if (MI->getOpcode() != TargetInstrInfo::LABEL) {
- SawPotentiallyThrowing |= MI->getDesc()->isCall();
+ SawPotentiallyThrowing |= MI->getDesc().isCall();
MachineBasicBlock::iterator I = BB->end();
while (I != BB->begin()) {
--I;
MachineBasicBlock::iterator I = BB->end();
while (I != BB->begin()) {
--I;
- if (!I->getDesc()->isBranch())
+ if (!I->getDesc().isBranch())
bool SeenCondBr = false;
for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
I != E; ++I) {
bool SeenCondBr = false;
for (MachineBasicBlock::iterator I = BBI.BB->begin(), E = BBI.BB->end();
I != E; ++I) {
- const TargetInstrDescriptor *TID = I->getDesc();
- if (TID->isNotDuplicable())
+ const TargetInstrDesc &TID = I->getDesc();
+ if (TID.isNotDuplicable())
BBI.CannotBeCopied = true;
bool isPredicated = TII->isPredicated(I);
BBI.CannotBeCopied = true;
bool isPredicated = TII->isPredicated(I);
- bool isCondBr = BBI.IsBrAnalyzable && TID->isConditionalBranch();
+ bool isCondBr = BBI.IsBrAnalyzable && TID.isConditionalBranch();
if (!isCondBr) {
if (!isPredicated)
if (!isCondBr) {
if (!isPredicated)
if (TII->DefinesPredicate(I, PredDefs))
BBI.ClobbersPred = true;
if (TII->DefinesPredicate(I, PredDefs))
BBI.ClobbersPred = true;
- if (!TID->isPredicable()) {
+ if (!TID.isPredicable()) {
BBI.IsUnpredicable = true;
return;
}
BBI.IsUnpredicable = true;
return;
}
bool IgnoreBr) {
for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
E = FromBBI.BB->end(); I != E; ++I) {
bool IgnoreBr) {
for (MachineBasicBlock::iterator I = FromBBI.BB->begin(),
E = FromBBI.BB->end(); I != E; ++I) {
- const TargetInstrDescriptor *TID = I->getDesc();
+ const TargetInstrDesc &TID = I->getDesc();
bool isPredicated = TII->isPredicated(I);
// Do not copy the end of the block branches.
bool isPredicated = TII->isPredicated(I);
// Do not copy the end of the block branches.
- if (IgnoreBr && !isPredicated && TID->isBranch())
+ if (IgnoreBr && !isPredicated && TID.isBranch())
break;
MachineInstr *MI = I->clone();
break;
MachineInstr *MI = I->clone();
return false;
isLoad = false;
return false;
isLoad = false;
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (TID->isImplicitDef() || tii_->isTriviallyReMaterializable(MI)) {
- isLoad = TID->isSimpleLoad();
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (TID.isImplicitDef() || tii_->isTriviallyReMaterializable(MI)) {
+ isLoad = TID.isSimpleLoad();
SmallVector<unsigned, 2> &Ops,
bool isSS, int Slot, unsigned Reg) {
unsigned MRInfo = 0;
SmallVector<unsigned, 2> &Ops,
bool isSS, int Slot, unsigned Reg) {
unsigned MRInfo = 0;
- const TargetInstrDescriptor *TID = MI->getDesc();
+ const TargetInstrDesc &TID = MI->getDesc();
// If it is an implicit def instruction, just delete it.
// If it is an implicit def instruction, just delete it.
- if (TID->isImplicitDef()) {
+ if (TID.isImplicitDef()) {
RemoveMachineInstrFromMaps(MI);
vrm.RemoveMachineInstrFromMaps(MI);
MI->eraseFromParent();
RemoveMachineInstrFromMaps(MI);
vrm.RemoveMachineInstrFromMaps(MI);
MI->eraseFromParent();
MRInfo |= (unsigned)VirtRegMap::isMod;
else {
// Filter out two-address use operand(s).
MRInfo |= (unsigned)VirtRegMap::isMod;
else {
// Filter out two-address use operand(s).
- if (TID->getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
+ if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1) {
MRInfo = VirtRegMap::isModRef;
continue;
}
MRInfo = VirtRegMap::isModRef;
continue;
}
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
- (DefIsReMat && (ReMatDefMI->getDesc()->isSimpleLoad()));
+ (DefIsReMat && (ReMatDefMI->getDesc().isSimpleLoad()));
bool IsFirstRange = true;
for (LiveInterval::Ranges::const_iterator
I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
bool IsFirstRange = true;
for (LiveInterval::Ranges::const_iterator
I = li.ranges.begin(), E = li.ranges.end(); I != E; ++I) {
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
int LdSlot = 0;
bool isLoadSS = DefIsReMat && tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
bool isLoad = isLoadSS ||
- (DefIsReMat && ReMatDefMI->getDesc()->isSimpleLoad());
+ (DefIsReMat && ReMatDefMI->getDesc().isSimpleLoad());
rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
rewriteInstructionsForSpills(li, TrySplit, I, ReMatOrigDefMI, ReMatDefMI,
Slot, LdSlot, isLoad, isLoadSS, DefIsReMat,
CanDelete, vrm, RegInfo, rc, ReMatIds, loopInfo,
int LdSlot = 0;
bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
// If the rematerializable def is a load, also try to fold it.
int LdSlot = 0;
bool isLoadSS = tii_->isLoadFromStackSlot(ReMatDefMI, LdSlot);
// If the rematerializable def is a load, also try to fold it.
- if (isLoadSS || ReMatDefMI->getDesc()->isSimpleLoad())
+ if (isLoadSS || ReMatDefMI->getDesc().isSimpleLoad())
Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
Ops, isLoadSS, LdSlot, VReg);
}
Folded = tryFoldMemoryOperand(MI, vrm, ReMatDefMI, index,
Ops, isLoadSS, LdSlot, VReg);
}
MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg);
assert(UseIdx != -1);
MachineInstr *LastUse = getInstructionFromIndex(LastUseIdx);
int UseIdx = LastUse->findRegisterUseOperandIdx(LI->reg);
assert(UseIdx != -1);
- if (LastUse->getDesc()->getOperandConstraint(UseIdx, TOI::TIED_TO) ==
+ if (LastUse->getDesc().getOperandConstraint(UseIdx, TOI::TIED_TO) ==
-1) {
LastUse->getOperand(UseIdx).setIsKill();
vrm.addKillPoint(LI->reg, LastUseIdx);
-1) {
LastUse->getOperand(UseIdx).setIsKill();
vrm.addKillPoint(LI->reg, LastUseIdx);
// Finally, if the last instruction in the block is a return, make sure to mark
// it as using all of the live-out values in the function.
// Finally, if the last instruction in the block is a return, make sure to mark
// it as using all of the live-out values in the function.
- if (!MBB->empty() && MBB->back().getDesc()->isReturn()) {
+ if (!MBB->empty() && MBB->back().getDesc().isReturn()) {
MachineInstr *Ret = &MBB->back();
for (MachineRegisterInfo::liveout_iterator
I = MF->getRegInfo().liveout_begin(),
MachineInstr *Ret = &MBB->back();
for (MachineRegisterInfo::liveout_iterator
I = MF->getRegInfo().liveout_begin(),
MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
iterator I = end();
MachineBasicBlock::iterator MachineBasicBlock::getFirstTerminator() {
iterator I = end();
- while (I != begin() && (--I)->getDesc()->isTerminator())
+ while (I != begin() && (--I)->getDesc().isTerminator())
- if (I != end() && !I->getDesc()->isTerminator()) ++I;
+ if (I != end() && !I->getDesc().isTerminator()) ++I;
MachineBasicBlock::iterator I = end();
while (I != begin()) {
--I;
MachineBasicBlock::iterator I = end();
while (I != begin()) {
--I;
- if (!I->getDesc()->isTerminator()) break;
+ if (!I->getDesc().isTerminator()) break;
// Scan the operands of this machine instruction, replacing any uses of Old
// with New.
// Scan the operands of this machine instruction, replacing any uses of Old
// with New.
/// MachineInstr ctor - This constructor create a MachineInstr and add the
/// implicit operands. It reserves space for number of operands specified by
/// MachineInstr ctor - This constructor create a MachineInstr and add the
/// implicit operands. It reserves space for number of operands specified by
-/// TargetInstrDescriptor or the numOperands if it is not zero. (for
+/// TargetInstrDesc or the numOperands if it is not zero. (for
/// instructions with variable number of operands).
/// instructions with variable number of operands).
-MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
+MachineInstr::MachineInstr(const TargetInstrDesc &tid, bool NoImp)
: TID(&tid), NumImplicitOps(0), Parent(0) {
if (!NoImp && TID->getImplicitDefs())
for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
: TID(&tid), NumImplicitOps(0), Parent(0) {
if (!NoImp && TID->getImplicitDefs())
for (const unsigned *ImpDefs = TID->getImplicitDefs(); *ImpDefs; ++ImpDefs)
/// MachineInstr is created and added to the end of the specified basic block.
///
MachineInstr::MachineInstr(MachineBasicBlock *MBB,
/// MachineInstr is created and added to the end of the specified basic block.
///
MachineInstr::MachineInstr(MachineBasicBlock *MBB,
- const TargetInstrDescriptor &tid)
+ const TargetInstrDesc &tid)
: TID(&tid), NumImplicitOps(0), Parent(0) {
assert(MBB && "Cannot use inserting ctor with null basic block!");
if (TID->ImplicitDefs)
: TID(&tid), NumImplicitOps(0), Parent(0) {
assert(MBB && "Cannot use inserting ctor with null basic block!");
if (TID->ImplicitDefs)
/// MachineInstr ctor - Copies MachineInstr arg exactly
///
MachineInstr::MachineInstr(const MachineInstr &MI) {
/// MachineInstr ctor - Copies MachineInstr arg exactly
///
MachineInstr::MachineInstr(const MachineInstr &MI) {
NumImplicitOps = MI.NumImplicitOps;
Operands.reserve(MI.getNumOperands());
NumImplicitOps = MI.NumImplicitOps;
Operands.reserve(MI.getNumOperands());
/// operand list that is used to represent the predicate. It returns -1 if
/// none is found.
int MachineInstr::findFirstPredOperandIdx() const {
/// operand list that is used to represent the predicate. It returns -1 if
/// none is found.
int MachineInstr::findFirstPredOperandIdx() const {
- const TargetInstrDescriptor *TID = getDesc();
- if (TID->isPredicable()) {
+ const TargetInstrDesc &TID = getDesc();
+ if (TID.isPredicable()) {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
for (unsigned i = 0, e = getNumOperands(); i != e; ++i)
- if (TID->OpInfo[i].isPredicate())
+ if (TID.OpInfo[i].isPredicate())
/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
/// to two addr elimination.
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
/// isRegReDefinedByTwoAddr - Returns true if the Reg re-definition is due
/// to two addr elimination.
bool MachineInstr::isRegReDefinedByTwoAddr(unsigned Reg) const {
- const TargetInstrDescriptor *TID = getDesc();
+ const TargetInstrDesc &TID = getDesc();
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO1 = getOperand(i);
if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
for (unsigned j = i+1; j < e; ++j) {
const MachineOperand &MO2 = getOperand(j);
if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
const MachineOperand &MO1 = getOperand(i);
if (MO1.isRegister() && MO1.isDef() && MO1.getReg() == Reg) {
for (unsigned j = i+1; j < e; ++j) {
const MachineOperand &MO2 = getOperand(j);
if (MO2.isRegister() && MO2.isUse() && MO2.getReg() == Reg &&
- TID->getOperandConstraint(j, TOI::TIED_TO) == (int)i)
+ TID.getOperandConstraint(j, TOI::TIED_TO) == (int)i)
/// copyPredicates - Copies predicate operand(s) from MI.
void MachineInstr::copyPredicates(const MachineInstr *MI) {
/// copyPredicates - Copies predicate operand(s) from MI.
void MachineInstr::copyPredicates(const MachineInstr *MI) {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (TID->isPredicable()) {
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (TID.isPredicable()) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
- if (TID->OpInfo[i].isPredicate()) {
+ if (TID.OpInfo[i].isPredicate()) {
// Predicated operands must be last operands.
addOperand(MI->getOperand(i));
}
// Predicated operands must be last operands.
addOperand(MI->getOperand(i));
}
++StartOp; // Don't print this operand again!
}
++StartOp; // Don't print this operand again!
}
+ OS << getDesc().getName();
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
if (i != StartOp)
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
if (i != StartOp)
bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
DEBUG({
DOUT << "--- Checking if we can hoist " << I;
bool MachineLICM::IsLoopInvariantInst(MachineInstr &I) {
DEBUG({
DOUT << "--- Checking if we can hoist " << I;
- if (I.getDesc()->ImplicitUses) {
+ if (I.getDesc().getImplicitUses()) {
DOUT << " * Instruction has implicit uses:\n";
const MRegisterInfo *MRI = TM->getRegisterInfo();
DOUT << " * Instruction has implicit uses:\n";
const MRegisterInfo *MRI = TM->getRegisterInfo();
- for (const unsigned *ImpUses = I.getDesc()->ImplicitUses;
+ for (const unsigned *ImpUses = I.getDesc().getImplicitUses();
*ImpUses; ++ImpUses)
DOUT << " -> " << MRI->getName(*ImpUses) << "\n";
}
*ImpUses; ++ImpUses)
DOUT << " -> " << MRI->getName(*ImpUses) << "\n";
}
- if (I.getDesc()->ImplicitDefs) {
+ if (I.getDesc().getImplicitDefs()) {
DOUT << " * Instruction has implicit defines:\n";
const MRegisterInfo *MRI = TM->getRegisterInfo();
DOUT << " * Instruction has implicit defines:\n";
const MRegisterInfo *MRI = TM->getRegisterInfo();
- for (const unsigned *ImpDefs = I.getDesc()->ImplicitDefs;
+ for (const unsigned *ImpDefs = I.getDesc().getImplicitDefs();
*ImpDefs; ++ImpDefs)
DOUT << " -> " << MRI->getName(*ImpDefs) << "\n";
}
*ImpDefs; ++ImpDefs)
DOUT << " -> " << MRI->getName(*ImpDefs) << "\n";
}
// Add code to restore the callee-save registers in each exiting block.
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
// If last instruction is a return instruction, add an epilogue.
// Add code to restore the callee-save registers in each exiting block.
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
// If last instruction is a return instruction, add an epilogue.
- if (!FI->empty() && FI->back().getDesc()->isReturn()) {
+ if (!FI->empty() && FI->back().getDesc().isReturn()) {
MBB = FI;
I = MBB->end(); --I;
// Skip over all terminator instructions, which are part of the return
// sequence.
MachineBasicBlock::iterator I2 = I;
MBB = FI;
I = MBB->end(); --I;
// Skip over all terminator instructions, which are part of the return
// sequence.
MachineBasicBlock::iterator I2 = I;
- while (I2 != MBB->begin() && (--I2)->getDesc()->isTerminator())
+ while (I2 != MBB->begin() && (--I2)->getDesc().isTerminator())
I = I2;
bool AtStart = I == MBB->begin();
I = I2;
bool AtStart = I == MBB->begin();
// Add epilogue to restore the callee-save registers in each exiting block
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
// Add epilogue to restore the callee-save registers in each exiting block
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
- if (!I->empty() && I->back().getDesc()->isReturn())
+ if (!I->empty() && I->back().getDesc().isReturn())
Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
}
}
Fn.getTarget().getRegisterInfo()->emitEpilogue(Fn, *I);
}
}
while (MII != MBB.end()) {
MachineInstr *MI = MII++;
MBBCurTime++;
while (MII != MBB.end()) {
MachineInstr *MI = MII++;
MBBCurTime++;
- const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
+ const TargetInstrDesc &TID = MI->getDesc();
DEBUG(DOUT << "\nTime=" << MBBCurTime << " Starting RegAlloc of: " << *MI;
DOUT << " Regs have values: ";
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
DEBUG(DOUT << "\nTime=" << MBBCurTime << " Starting RegAlloc of: " << *MI;
DOUT << " Regs have values: ";
for (unsigned i = 0; i != RegInfo->getNumRegs(); ++i)
}
// Loop over the implicit defs, spilling them as well.
}
// Loop over the implicit defs, spilling them as well.
- if (TID.ImplicitDefs) {
- for (const unsigned *ImplicitDefs = TID.ImplicitDefs;
+ if (TID.getImplicitDefs()) {
+ for (const unsigned *ImplicitDefs = TID.getImplicitDefs();
*ImplicitDefs; ++ImplicitDefs) {
unsigned Reg = *ImplicitDefs;
if (PhysRegsUsed[Reg] != -2) {
*ImplicitDefs; ++ImplicitDefs) {
unsigned Reg = *ImplicitDefs;
if (PhysRegsUsed[Reg] != -2) {
// Otherwise, sequentially allocate each instruction in the MBB.
while (MII != MBB.end()) {
MachineInstr *MI = MII++;
// Otherwise, sequentially allocate each instruction in the MBB.
while (MII != MBB.end()) {
MachineInstr *MI = MII++;
- const TargetInstrDescriptor &TID = TII.get(MI->getOpcode());
+ const TargetInstrDesc &TID = MI->getDesc();
DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
DOUT << " Regs have values: ";
for (unsigned i = 0; i != MRI->getNumRegs(); ++i)
DEBUG(DOUT << "\nStarting RegAlloc of: " << *MI;
DOUT << " Regs have values: ";
for (unsigned i = 0; i != MRI->getNumRegs(); ++i)
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
// This is a preliminary pass that will invalidate any registers that are
// used by the instruction (including implicit uses).
- const TargetInstrDescriptor &Desc = *MI->getDesc();
+ const TargetInstrDesc &Desc = MI->getDesc();
const unsigned *Regs;
if (Desc.ImplicitUses) {
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
const unsigned *Regs;
if (Desc.ImplicitUses) {
for (Regs = Desc.ImplicitUses; *Regs; ++Regs)
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
unsigned physReg = Virt2PhysRegMap[virtualReg];
if (physReg == 0) {
if (op.isDef()) {
- int TiedOp = MI->getDesc()->findTiedToSrcOperand(i);
+ int TiedOp = Desc.findTiedToSrcOperand(i);
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
} else {
if (TiedOp == -1) {
physReg = getFreeReg(virtualReg);
} else {
}
MachineInstr *MI = MBBI;
}
MachineInstr *MI = MBBI;
+ const TargetInstrDesc &TID = MI->getDesc();
// Reaching a terminator instruction. Restore a scavenged register (which
// must be life out.
// Reaching a terminator instruction. Restore a scavenged register (which
// must be life out.
- if (MI->getDesc()->isTerminator())
+ if (TID.isTerminator())
restoreScavengedReg();
// Process uses first.
restoreScavengedReg();
// Process uses first.
setUnused(ChangedRegs);
// Process defs.
setUnused(ChangedRegs);
// Process defs.
- const TargetInstrDescriptor *TID = MI->getDesc();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister() || !MO.isDef())
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister() || !MO.isDef())
continue;
}
// Skip two-address destination operand.
continue;
}
// Skip two-address destination operand.
- if (TID->findTiedToSrcOperand(i) != -1) {
+ if (TID.findTiedToSrcOperand(i) != -1) {
assert(isUsed(Reg) && "Using an undefined register!");
continue;
}
assert(isUsed(Reg) && "Using an undefined register!");
continue;
}
MachineInstr *MI = MBBI;
// Process defs first.
MachineInstr *MI = MBBI;
// Process defs first.
- const TargetInstrDescriptor *TID = MI->getDesc();
+ const TargetInstrDesc &TID = MI->getDesc();
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister() || !MO.isDef())
continue;
// Skip two-address destination operand.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
const MachineOperand &MO = MI->getOperand(i);
if (!MO.isRegister() || !MO.isDef())
continue;
// Skip two-address destination operand.
- if (TID->findTiedToSrcOperand(i) != -1)
+ if (TID.findTiedToSrcOperand(i) != -1)
continue;
unsigned Reg = MO.getReg();
assert(isUsed(Reg));
continue;
unsigned Reg = MO.getReg();
assert(isUsed(Reg));
unsigned ResNo = Use->getOperand(2).ResNo;
if (Def->isTargetOpcode()) {
unsigned ResNo = Use->getOperand(2).ResNo;
if (Def->isTargetOpcode()) {
- const TargetInstrDescriptor &II = TII->get(Def->getTargetOpcode());
+ const TargetInstrDesc &II = TII->get(Def->getTargetOpcode());
if (ResNo >= II.getNumDefs() &&
II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
PhysReg = Reg;
if (ResNo >= II.getNumDefs() &&
II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) {
PhysReg = Reg;
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
if (MainNode->isTargetOpcode()) {
unsigned Opc = MainNode->getTargetOpcode();
- const TargetInstrDescriptor &TID = TII->get(Opc);
+ const TargetInstrDesc &TID = TII->get(Opc);
for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
SU->isTwoAddress = true;
for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
SU->isTwoAddress = true;
static const TargetRegisterClass *getInstrOperandRegClass(
const MRegisterInfo *MRI,
const TargetInstrInfo *TII,
static const TargetRegisterClass *getInstrOperandRegClass(
const MRegisterInfo *MRI,
const TargetInstrInfo *TII,
- const TargetInstrDescriptor *II,
+ const TargetInstrDesc &II,
- if (Op >= II->getNumOperands()) {
- assert(II->isVariadic() && "Invalid operand # of instruction");
+ if (Op >= II.getNumOperands()) {
+ assert(II.isVariadic() && "Invalid operand # of instruction");
- if (II->OpInfo[Op].isLookupPtrRegClass())
+ if (II.OpInfo[Op].isLookupPtrRegClass())
return TII->getPointerRegClass();
return TII->getPointerRegClass();
- return MRI->getRegClass(II->OpInfo[Op].RegClass);
+ return MRI->getRegClass(II.OpInfo[Op].RegClass);
}
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
}
void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
MachineInstr *MI,
void ScheduleDAG::CreateVirtualRegisters(SDNode *Node,
MachineInstr *MI,
- const TargetInstrDescriptor &II,
+ const TargetInstrDesc &II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
for (unsigned i = 0; i < II.getNumDefs(); ++i) {
// If the specific node value is only used by a CopyToReg and the dest reg
DenseMap<SDOperand, unsigned> &VRBaseMap) {
for (unsigned i = 0; i < II.getNumDefs(); ++i) {
// If the specific node value is only used by a CopyToReg and the dest reg
// Create the result registers for this node and add the result regs to
// the machine instruction.
if (VRBase == 0) {
// Create the result registers for this node and add the result regs to
// the machine instruction.
if (VRBase == 0) {
- const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, &II, i);
+ const TargetRegisterClass *RC = getInstrOperandRegClass(MRI, TII, II, i);
assert(RC && "Isn't a register operand!");
VRBase = RegInfo.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
assert(RC && "Isn't a register operand!");
VRBase = RegInfo.createVirtualRegister(RC);
MI->addOperand(MachineOperand::CreateReg(VRBase, true));
/// assertions only.
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
/// assertions only.
void ScheduleDAG::AddOperand(MachineInstr *MI, SDOperand Op,
unsigned IIOpNum,
- const TargetInstrDescriptor *II,
+ const TargetInstrDesc *II,
DenseMap<SDOperand, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
DenseMap<SDOperand, unsigned> &VRBaseMap) {
if (Op.isTargetOpcode()) {
// Note that this case is redundant with the final else block, but we
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
- const TargetInstrDescriptor *TID = MI->getDesc();
- bool isOptDef = (IIOpNum < TID->getNumOperands())
- ? (TID->OpInfo[IIOpNum].isOptionalDef()) : false;
+ const TargetInstrDesc &TID = MI->getDesc();
+ bool isOptDef = (IIOpNum < TID.getNumOperands())
+ ? (TID.OpInfo[IIOpNum].isOptionalDef()) : false;
MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
MI->addOperand(MachineOperand::CreateReg(VReg, isOptDef));
// Verify that it is right.
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
- getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+ getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
if (VRC != RC) {
assert(RC && "Don't have operand info for this instruction!");
const TargetRegisterClass *VRC = RegInfo.getRegClass(VReg);
if (VRC != RC) {
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
assert(MRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
if (II) {
const TargetRegisterClass *RC =
- getInstrOperandRegClass(MRI, TII, II, IIOpNum);
+ getInstrOperandRegClass(MRI, TII, *II, IIOpNum);
assert(RC && "Don't have operand info for this instruction!");
assert(RegInfo.getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
assert(RC && "Don't have operand info for this instruction!");
assert(RegInfo.getRegClass(VReg) == RC &&
"Register class of operand and regclass of use don't agree!");
- const TargetInstrDescriptor &II = TII->get(Opc);
+ const TargetInstrDesc &II = TII->get(Opc);
unsigned NumResults = CountResults(Node);
unsigned NodeOperands = CountOperands(Node);
unsigned NumResults = CountResults(Node);
unsigned NodeOperands = CountOperands(Node);
if (!SU || !SU->Node) continue;
if (SU->isCommutable) {
unsigned Opc = SU->Node->getTargetOpcode();
if (!SU || !SU->Node) continue;
if (SU->isCommutable) {
unsigned Opc = SU->Node->getTargetOpcode();
- const TargetInstrDescriptor &TID = TII->get(Opc);
+ const TargetInstrDesc &TID = TII->get(Opc);
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = CountOperands(SU->Node);
for (unsigned j = 0; j != NumOps; ++j) {
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = CountOperands(SU->Node);
for (unsigned j = 0; j != NumOps; ++j) {
SUnit *NewSU = NewSUnit(N);
SUnitMap[N].push_back(NewSU);
SUnit *NewSU = NewSUnit(N);
SUnitMap[N].push_back(NewSU);
- const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
+ const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
NewSU->isTwoAddress = true;
for (unsigned i = 0; i != TID.getNumOperands(); ++i) {
if (TID.getOperandConstraint(i, TOI::TIED_TO) != -1) {
NewSU->isTwoAddress = true;
/// FIXME: Move to SelectionDAG?
static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const TargetInstrInfo *TII) {
/// FIXME: Move to SelectionDAG?
static MVT::ValueType getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const TargetInstrInfo *TII) {
- const TargetInstrDescriptor &TID = TII->get(N->getTargetOpcode());
+ const TargetInstrDesc &TID = TII->get(N->getTargetOpcode());
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
unsigned NumRes = TID.getNumDefs();
for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
unsigned NumRes = TID.getNumDefs();
for (const unsigned *ImpDef = TID.getImplicitDefs(); *ImpDef; ++ImpDef) {
SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
if (!Node || !Node->isTargetOpcode())
continue;
SDNode *Node = (i == 0) ? SU->Node : SU->FlaggedNodes[i-1];
if (!Node || !Node->isTargetOpcode())
continue;
- const TargetInstrDescriptor &TID = TII->get(Node->getTargetOpcode());
+ const TargetInstrDesc &TID = TII->get(Node->getTargetOpcode());
if (!TID.ImplicitDefs)
continue;
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
if (!TID.ImplicitDefs)
continue;
for (const unsigned *Reg = TID.ImplicitDefs; *Reg; ++Reg) {
bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
if (SU->isTwoAddress) {
unsigned Opc = SU->Node->getTargetOpcode();
bool BURegReductionPriorityQueue<SF>::canClobber(SUnit *SU, SUnit *Op) {
if (SU->isTwoAddress) {
unsigned Opc = SU->Node->getTargetOpcode();
- const TargetInstrDescriptor &TID = TII->get(Opc);
+ const TargetInstrDesc &TID = TII->get(Opc);
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
for (unsigned i = 0; i != NumOps; ++i) {
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = ScheduleDAG::CountOperands(SU->Node);
for (unsigned i = 0; i != NumOps; ++i) {
continue;
unsigned Opc = Node->getTargetOpcode();
continue;
unsigned Opc = Node->getTargetOpcode();
- const TargetInstrDescriptor &TID = TII->get(Opc);
+ const TargetInstrDesc &TID = TII->get(Opc);
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = ScheduleDAG::CountOperands(Node);
for (unsigned j = 0; j != NumOps; ++j) {
unsigned NumRes = TID.getNumDefs();
unsigned NumOps = ScheduleDAG::CountOperands(Node);
for (unsigned j = 0; j != NumOps; ++j) {
bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const {
bool MadeChange = false;
bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
const std::vector<MachineOperand> &Pred) const {
bool MadeChange = false;
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (TID->isPredicable()) {
- for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
- if (TID->OpInfo[i].isPredicate()) {
- MachineOperand &MO = MI->getOperand(i);
- if (MO.isReg()) {
- MO.setReg(Pred[j].getReg());
- MadeChange = true;
- } else if (MO.isImm()) {
- MO.setImm(Pred[j].getImm());
- MadeChange = true;
- } else if (MO.isMBB()) {
- MO.setMBB(Pred[j].getMBB());
- MadeChange = true;
- }
- ++j;
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.isPredicable())
+ return false;
+
+ for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
+ if (TID.OpInfo[i].isPredicate()) {
+ MachineOperand &MO = MI->getOperand(i);
+ if (MO.isReg()) {
+ MO.setReg(Pred[j].getReg());
+ MadeChange = true;
+ } else if (MO.isImm()) {
+ MO.setImm(Pred[j].getImm());
+ MadeChange = true;
+ } else if (MO.isMBB()) {
+ MO.setMBB(Pred[j].getMBB());
+ MadeChange = true;
mbbi != mbbe; ++mbbi) {
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
mi != me; ++mi) {
mbbi != mbbe; ++mbbi) {
for (MachineBasicBlock::iterator mi = mbbi->begin(), me = mbbi->end();
mi != me; ++mi) {
- const TargetInstrDescriptor *TID = mi->getDesc();
+ const TargetInstrDesc &TID = mi->getDesc();
- for (unsigned si = 1, e = TID->getNumOperands(); si < e; ++si) {
- int ti = TID->getOperandConstraint(si, TOI::TIED_TO);
+ for (unsigned si = 1, e = TID.getNumOperands(); si < e; ++si) {
+ int ti = TID.getOperandConstraint(si, TOI::TIED_TO);
// so, swap the B and C operands. This makes the live ranges of A
// and C joinable.
// FIXME: This code also works for A := B op C instructions.
// so, swap the B and C operands. This makes the live ranges of A
// and C joinable.
// FIXME: This code also works for A := B op C instructions.
- if (TID->isCommutable() && mi->getNumOperands() >= 3) {
+ if (TID.isCommutable() && mi->getNumOperands() >= 3) {
assert(mi->getOperand(3-si).isRegister() &&
"Not a proper commutative instruction!");
unsigned regC = mi->getOperand(3-si).getReg();
assert(mi->getOperand(3-si).isRegister() &&
"Not a proper commutative instruction!");
unsigned regC = mi->getOperand(3-si).getReg();
// If this instruction is potentially convertible to a true
// three-address instruction,
// If this instruction is potentially convertible to a true
// three-address instruction,
- if (TID->isConvertibleTo3Addr()) {
+ if (TID.isConvertibleTo3Addr()) {
// FIXME: This assumes there are no more operands which are tied
// to another register.
#ifndef NDEBUG
// FIXME: This assumes there are no more operands which are tied
// to another register.
#ifndef NDEBUG
- for (unsigned i = si+1, e = TID->getNumOperands(); i < e; ++i)
- assert(TID->getOperandConstraint(i, TOI::TIED_TO) == -1);
+ for (unsigned i = si+1, e = TID.getNumOperands(); i < e; ++i)
+ assert(TID.getOperandConstraint(i, TOI::TIED_TO) == -1);
#endif
if (MachineInstr *New = TII.convertToThreeAddress(mbbi, mi, LV)) {
#endif
if (MachineInstr *New = TII.convertToThreeAddress(mbbi, mi, LV)) {
/// over.
static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
std::vector<MachineOperand*> &KillOps) {
/// over.
static void UpdateKills(MachineInstr &MI, BitVector &RegKills,
std::vector<MachineOperand*> &KillOps) {
- const TargetInstrDescriptor *TID = MI.getDesc();
+ const TargetInstrDesc &TID = MI.getDesc();
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isRegister() || !MO.isUse())
for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
MachineOperand &MO = MI.getOperand(i);
if (!MO.isRegister() || !MO.isUse())
KillOps[Reg]->setIsKill(false);
KillOps[Reg] = NULL;
RegKills.reset(Reg);
KillOps[Reg]->setIsKill(false);
KillOps[Reg] = NULL;
RegKills.reset(Reg);
- if (i < TID->getNumOperands() &&
- TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
+ if (i < TID.getNumOperands() &&
+ TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
// Unless it's a two-address operand, this is the new kill.
MO.setIsKill();
}
// Unless it's a two-address operand, this is the new kill.
MO.setIsKill();
}
NextMII = next(MII);
MachineInstr &MI = *MII;
NextMII = next(MII);
MachineInstr &MI = *MII;
- const TargetInstrDescriptor *TID = MI.getDesc();
+ const TargetInstrDesc &TID = MI.getDesc();
// Insert restores here if asked to.
if (VRM.isRestorePt(&MI)) {
// Insert restores here if asked to.
if (VRM.isRestorePt(&MI)) {
// aren't allowed to modify the reused register. If none of these cases
// apply, reuse it.
bool CanReuse = true;
// aren't allowed to modify the reused register. If none of these cases
// apply, reuse it.
bool CanReuse = true;
- int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
+ int ti = TID.getOperandConstraint(i, TOI::TIED_TO);
if (ti != -1 &&
MI.getOperand(ti).isRegister() &&
MI.getOperand(ti).getReg() == VirtReg) {
if (ti != -1 &&
MI.getOperand(ti).isRegister() &&
MI.getOperand(ti).getReg() == VirtReg) {
Spills.addAvailable(SSorRMId, &MI, PhysReg);
// Assumes this is the last use. IsKill will be unset if reg is reused
// unless it's a two-address operand.
Spills.addAvailable(SSorRMId, &MI, PhysReg);
// Assumes this is the last use. IsKill will be unset if reg is reused
// unless it's a two-address operand.
- if (TID->getOperandConstraint(i, TOI::TIED_TO) == -1)
+ if (TID.getOperandConstraint(i, TOI::TIED_TO) == -1)
MI.getOperand(i).setIsKill();
unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
MI.getOperand(i).setReg(RReg);
MI.getOperand(i).setIsKill();
unsigned RReg = SubIdx ? MRI->getSubReg(PhysReg, SubIdx) : PhysReg;
MI.getOperand(i).setReg(RReg);
// If this def is part of a two-address operand, make sure to execute
// the store from the correct physical register.
unsigned PhysReg;
// If this def is part of a two-address operand, make sure to execute
// the store from the correct physical register.
unsigned PhysReg;
- int TiedOp = MI.getDesc()->findTiedToSrcOperand(i);
+ int TiedOp = MI.getDesc().findTiedToSrcOperand(i);
if (TiedOp != -1) {
PhysReg = MI.getOperand(TiedOp).getReg();
if (SubIdx) {
if (TiedOp != -1) {
PhysReg = MI.getOperand(TiedOp).getReg();
if (SubIdx) {
void emitInstruction(const MachineInstr &MI);
int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
void emitInstruction(const MachineInstr &MI);
int getMachineOpValue(const MachineInstr &MI, unsigned OpIndex);
- unsigned getBaseOpcodeFor(const TargetInstrDescriptor *TID);
+ unsigned getBaseOpcodeFor(const TargetInstrDesc &TID);
unsigned getBinaryCodeForInstr(const MachineInstr &MI);
void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
unsigned getBinaryCodeForInstr(const MachineInstr &MI);
void emitGlobalAddressForCall(GlobalValue *GV, bool DoesntNeedStub);
}
/// getBaseOpcodeFor - Return the opcode value
}
/// getBaseOpcodeFor - Return the opcode value
-unsigned Emitter::getBaseOpcodeFor(const TargetInstrDescriptor *TID) {
- return (TID->TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
+unsigned Emitter::getBaseOpcodeFor(const TargetInstrDesc &TID) {
+ return (TID.TSFlags & ARMII::OpcodeMask) >> ARMII::OpcodeShift;
}
/// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
}
/// getShiftOp - Verify which is the shift opcode (bit[6:5]) of the
}
unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
}
unsigned Emitter::getBinaryCodeForInstr(const MachineInstr &MI) {
- const TargetInstrDescriptor *Desc = MI.getDesc();
- unsigned opcode = Desc->Opcode;
+ const TargetInstrDesc &Desc = MI.getDesc();
+ unsigned opcode = Desc.Opcode;
// initial instruction mask
unsigned Value = 0xE0000000;
unsigned op;
// initial instruction mask
unsigned Value = 0xE0000000;
unsigned op;
- switch (Desc->TSFlags & ARMII::AddrModeMask) {
+ switch (Desc.TSFlags & ARMII::AddrModeMask) {
case ARMII::AddrModeNone: {
case ARMII::AddrModeNone: {
- switch(Desc->TSFlags & ARMII::FormMask) {
+ switch(Desc.TSFlags & ARMII::FormMask) {
default: {
assert(0 && "Unknown instruction subtype!");
// treat special instruction CLZ
default: {
assert(0 && "Unknown instruction subtype!");
// treat special instruction CLZ
unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
Value |= BaseOpcode << 4;
unsigned char BaseOpcode = getBaseOpcodeFor(Desc);
Value |= BaseOpcode << 4;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = (Desc.TSFlags & ARMII::FormMask);
if (Format == ARMII::MulSMUL)
Value |= 1 << 22;
if (Format == ARMII::MulSMUL)
Value |= 1 << 22;
// treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
// MOVrx.
// treat 3 special instructions: MOVsra_flag, MOVsrl_flag and
// MOVrx.
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
if (Format == ARMII::DPRdMisc) {
Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
Value |= getMachineOpValue(MI,1);
if (Format == ARMII::DPRdMisc) {
Value |= getMachineOpValue(MI,0) << ARMII::RegRdShift;
Value |= getMachineOpValue(MI,1);
// bit 26 is always 1
Value |= 1 << 26;
// bit 26 is always 1
Value |= 1 << 26;
- unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+ unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
// if the instruction uses offset addressing or pre-indexed addressing,
// set bit P(24) to 1
if (Index == ARMII::IndexModePre || Index == 0)
// if the instruction uses offset addressing or pre-indexed addressing,
// set bit P(24) to 1
if (Index == ARMII::IndexModePre || Index == 0)
if (Index == ARMII::IndexModePre)
Value |= 1 << 21;
if (Index == ARMII::IndexModePre)
Value |= 1 << 21;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
// If it is a load instruction (except LDRD), set bit L(20) to 1
if (Format == ARMII::LdFrm)
Value |= 1 << ARMII::L_BitShift;
// If it is a load instruction (except LDRD), set bit L(20) to 1
if (Format == ARMII::LdFrm)
Value |= 1 << ARMII::L_BitShift;
break;
}
case ARMII::AddrMode3: {
break;
}
case ARMII::AddrMode3: {
-
- unsigned Index = (Desc->TSFlags & ARMII::IndexModeMask);
+ unsigned Index = Desc.TSFlags & ARMII::IndexModeMask;
// if the instruction uses offset addressing or pre-indexed addressing,
// set bit P(24) to 1
if (Index == ARMII::IndexModePre || Index == 0)
Value |= 1 << ARMII::IndexShift;
// if the instruction uses offset addressing or pre-indexed addressing,
// set bit P(24) to 1
if (Index == ARMII::IndexModePre || Index == 0)
Value |= 1 << ARMII::IndexShift;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
// If it is a load instruction (except LDRD), set bit L(20) to 1
if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
Value |= 1 << ARMII::L_BitShift;
// If it is a load instruction (except LDRD), set bit L(20) to 1
if (Format == ARMII::LdFrm && opcode != ARM::LDRD)
Value |= 1 << ARMII::L_BitShift;
// bit 27 is always 1
Value |= 1 << 27;
// bit 27 is always 1
Value |= 1 << 27;
- unsigned Format = (Desc->TSFlags & ARMII::FormMask);
+ unsigned Format = Desc.TSFlags & ARMII::FormMask;
// if it is a load instr, set bit L(20) to 1
if (Format == ARMII::LdFrm)
Value |= 1 << ARMII::L_BitShift;
// if it is a load instr, set bit L(20) to 1
if (Format == ARMII::LdFrm)
Value |= 1 << ARMII::L_BitShift;
MBBSize += ARM::GetInstSize(I);
int Opc = I->getOpcode();
MBBSize += ARM::GetInstSize(I);
int Opc = I->getOpcode();
- if (I->getDesc()->isBranch()) {
+ if (I->getDesc().isBranch()) {
bool isCond = false;
unsigned Bits = 0;
unsigned Scale = 1;
bool isCond = false;
unsigned Bits = 0;
unsigned Scale = 1;
// Basic size info comes from the TSFlags field.
unsigned Bits = 0;
unsigned Scale = 1;
// Basic size info comes from the TSFlags field.
unsigned Bits = 0;
unsigned Scale = 1;
- unsigned TSFlags = I->getDesc()->TSFlags;
+ unsigned TSFlags = I->getDesc().TSFlags;
switch (TSFlags & ARMII::AddrModeMask) {
default:
// Constant pool entries can reach anything.
switch (TSFlags & ARMII::AddrModeMask) {
default:
// Constant pool entries can reach anything.
return true;
case ARM::MOVr:
case ARM::tMOVr:
return true;
case ARM::MOVr:
case ARM::tMOVr:
- assert(MI.getDesc()->getNumOperands() >= 2 &&
+ assert(MI.getDesc().getNumOperands() >= 2 &&
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
MI.getOperand(0).isRegister() &&
MI.getOperand(1).isRegister() &&
"Invalid ARM MOV instruction");
return NULL;
MachineInstr *MI = MBBI;
return NULL;
MachineInstr *MI = MBBI;
- unsigned TSFlags = MI->getDesc()->TSFlags;
+ unsigned TSFlags = MI->getDesc().TSFlags;
bool isPre = false;
switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
default: return NULL;
bool isPre = false;
switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
default: return NULL;
MachineInstr *UpdateMI = NULL;
MachineInstr *MemMI = NULL;
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
MachineInstr *UpdateMI = NULL;
MachineInstr *MemMI = NULL;
unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
- const TargetInstrDescriptor *TID = MI->getDesc();
- unsigned NumOps = TID->getNumOperands();
- bool isLoad = TID->isSimpleLoad();
+ const TargetInstrDesc &TID = MI->getDesc();
+ unsigned NumOps = TID.getNumOperands();
+ bool isLoad = TID.isSimpleLoad();
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
const MachineOperand &Base = MI->getOperand(2);
const MachineOperand &Offset = MI->getOperand(NumOps-3);
const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
const MachineOperand &Base = MI->getOperand(2);
const MachineOperand &Offset = MI->getOperand(NumOps-3);
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
bool ARMInstrInfo::DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (!TID->getImplicitDefs() && !TID->hasOptionalDef())
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.getImplicitDefs() && !TID.hasOptionalDef())
return false;
bool Found = false;
return false;
bool Found = false;
const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
// Basic size info comes from the TSFlags field.
const TargetAsmInfo *TAI = MF->getTarget().getTargetAsmInfo();
// Basic size info comes from the TSFlags field.
- const TargetInstrDescriptor *TID = MI->getDesc();
- unsigned TSFlags = TID->TSFlags;
+ const TargetInstrDesc &TID = MI->getDesc();
+ unsigned TSFlags = TID.TSFlags;
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
default:
switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
default:
case ARM::tBR_JTr: {
// These are jumptable branches, i.e. a branch followed by an inlined
// jumptable. The size is 4 + 4 * number of entries.
case ARM::tBR_JTr: {
// These are jumptable branches, i.e. a branch followed by an inlined
// jumptable. The size is 4 + 4 * number of entries.
- unsigned NumOps = TID->getNumOperands();
+ unsigned NumOps = TID.getNumOperands();
- MI->getOperand(NumOps - (TID->isPredicable() ? 3 : 2));
+ MI->getOperand(NumOps - (TID.isPredicable() ? 3 : 2));
unsigned JTI = JTOP.getIndex();
MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
unsigned JTI = JTOP.getIndex();
MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
unsigned Base = MBBI->getOperand(1).getReg();
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
unsigned Base = MBBI->getOperand(1).getReg();
unsigned PredReg = 0;
ARMCC::CondCodes Pred = getInstrPredicate(MBBI, PredReg);
- const TargetInstrDescriptor *TID = MBBI->getDesc();
- unsigned OffField = MBBI->getOperand(TID->getNumOperands()-3).getImm();
+ unsigned NumOperands = MBBI->getDesc().getNumOperands();
+ unsigned OffField = MBBI->getOperand(NumOperands-3).getImm();
int Offset = isAM2
? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
if (isAM2) {
int Offset = isAM2
? ARM_AM::getAM2Offset(OffField) : ARM_AM::getAM5Offset(OffField) * 4;
if (isAM2) {
}
unsigned Opcode = MI.getOpcode();
}
unsigned Opcode = MI.getOpcode();
- const TargetInstrDescriptor &Desc = *MI.getDesc();
+ const TargetInstrDesc &Desc = MI.getDesc();
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
bool isSub = false;
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
bool isSub = false;
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isFrameIndex()) {
unsigned Opcode = I->getOpcode();
for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
if (I->getOperand(i).isFrameIndex()) {
unsigned Opcode = I->getOpcode();
- const TargetInstrDescriptor &Desc = TII.get(Opcode);
+ const TargetInstrDesc &Desc = TII.get(Opcode);
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
if (AddrMode == ARMII::AddrMode3) {
Limit = (1 << 8) - 1;
unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
if (AddrMode == ARMII::AddrMode3) {
Limit = (1 << 8) - 1;
{
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
{
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
- if (I->getDesc()->hasDelaySlot()) {
+ if (I->getDesc().hasDelaySlot()) {
MachineBasicBlock::iterator J = I;
++J;
BuildMI(MBB, J, TII->get(Mips::NOP));
MachineBasicBlock::iterator J = I;
++J;
BuildMI(MBB, J, TII->get(Mips::NOP));
// If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
// If there is only one terminator instruction, process it.
unsigned LastOpc = LastInst->getOpcode();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
- if (!LastInst->getDesc()->isBranch())
+ if (!LastInst->getDesc().isBranch())
return true;
// Unconditional branch
return true;
// Unconditional branch
} else {
// Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
} else {
// Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
- const TargetInstrDescriptor &TID = get(Opc);
+ const TargetInstrDesc &TID = get(Opc);
if (TID.getNumOperands() == 3)
BuildMI(&MBB, TID).addReg(Cond[1].getReg())
if (TID.getNumOperands() == 3)
BuildMI(&MBB, TID).addReg(Cond[1].getReg())
// Two-way Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
// Two-way Conditional branch.
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
- const TargetInstrDescriptor &TID = get(Opc);
+ const TargetInstrDesc &TID = get(Opc);
if (TID.getNumOperands() == 3)
if (TID.getNumOperands() == 3)
- BuildMI(&MBB, TID).addReg(Cond[1].getReg())
- .addReg(Cond[2].getReg())
+ BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
- BuildMI(&MBB, TID).addReg(Cond[1].getReg())
- .addMBB(TBB);
+ BuildMI(&MBB, TID).addReg(Cond[1].getReg()).addMBB(TBB);
BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
return 2;
BuildMI(&MBB, get(Mips::J)).addMBB(FBB);
return 2;
}
Opcode -= ISD::BUILTIN_OP_END;
}
Opcode -= ISD::BUILTIN_OP_END;
- const TargetInstrDescriptor &TID = TII.get(Opcode);
+ const TargetInstrDesc &TID = TII.get(Opcode);
isLoad = TID.isSimpleLoad();
isStore = TID.mayStore();
isLoad = TID.isSimpleLoad();
isStore = TID.mayStore();
// Find all return blocks, outputting a restore in each epilog.
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
// Find all return blocks, outputting a restore in each epilog.
for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
- if (!BB->empty() && BB->back().getDesc()->isReturn()) {
+ if (!BB->empty() && BB->back().getDesc().isReturn()) {
IP = BB->end(); --IP;
// Skip over all terminator instructions, which are part of the return
// sequence.
MachineBasicBlock::iterator I2 = IP;
IP = BB->end(); --IP;
// Skip over all terminator instructions, which are part of the return
// sequence.
MachineBasicBlock::iterator I2 = IP;
- while (I2 != BB->begin() && (--I2)->getDesc()->isTerminator())
+ while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
IP = I2;
// Emit: MTVRSAVE InVRSave
IP = I2;
// Emit: MTVRSAVE InVRSave
// epilog blocks.
for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
// epilog blocks.
for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
// If last instruction is a return instruction, add an epilogue
- if (!I->empty() && I->back().getDesc()->isReturn()) {
+ if (!I->empty() && I->back().getDesc().isReturn()) {
bool FoundIt = false;
for (MBBI = I->end(); MBBI != I->begin(); ) {
--MBBI;
bool FoundIt = false;
for (MBBI = I->end(); MBBI != I->begin(); ) {
--MBBI;
bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
bool Filler::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
bool Changed = false;
for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
- if (I->getDesc()->hasDelaySlot()) {
+ if (I->getDesc().hasDelaySlot()) {
MachineBasicBlock::iterator J = I;
++J;
BuildMI(MBB, J, TII->get(SP::NOP));
MachineBasicBlock::iterator J = I;
++J;
BuildMI(MBB, J, TII->get(SP::NOP));
/// findTiedToSrcOperand - Returns the operand that is tied to the specified
/// dest operand. Returns -1 if there isn't one.
/// findTiedToSrcOperand - Returns the operand that is tied to the specified
/// dest operand. Returns -1 if there isn't one.
-int TargetInstrDescriptor::findTiedToSrcOperand(unsigned OpNum) const {
+int TargetInstrDesc::findTiedToSrcOperand(unsigned OpNum) const {
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
if (i == OpNum)
continue;
for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
if (i == OpNum)
continue;
-TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
+TargetInstrInfo::TargetInstrInfo(const TargetInstrDesc* Desc,
- : desc(Desc), NumOpcodes(numOpcodes) {
+ : Descriptors(Desc), NumOpcodes(numOpcodes) {
}
TargetInstrInfo::~TargetInstrInfo() {
}
bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
}
TargetInstrInfo::~TargetInstrInfo() {
}
bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (!TID->isTerminator()) return false;
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.isTerminator()) return false;
// Conditional branch is a special case.
// Conditional branch is a special case.
- if (TID->isBranch() && !TID->isBarrier())
+ if (TID.isBranch() && !TID.isBarrier())
- if (!TID->isPredicable())
+ if (!TID.isPredicable())
return true;
return !isPredicated(MI);
}
return true;
return !isPredicated(MI);
}
}
void emitInstruction(const MachineInstr &MI,
}
void emitInstruction(const MachineInstr &MI,
- const TargetInstrDescriptor *Desc);
+ const TargetInstrDesc *Desc);
private:
void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
private:
void emitPCRelativeBlockAddress(MachineBasicBlock *MBB);
MCE.StartMachineBasicBlock(MBB);
for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
MCE.StartMachineBasicBlock(MBB);
for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
I != E; ++I) {
- const TargetInstrDescriptor *Desc = I->getDesc();
- emitInstruction(*I, Desc);
+ const TargetInstrDesc &Desc = I->getDesc();
+ emitInstruction(*I, &Desc);
// MOVPC32r is basically a call plus a pop instruction.
// MOVPC32r is basically a call plus a pop instruction.
- if (Desc->Opcode == X86::MOVPC32r)
+ if (Desc.getOpcode() == X86::MOVPC32r)
emitInstruction(*I, &II->get(X86::POP32r));
NumEmitted++; // Keep track of the # of mi's emitted
}
emitInstruction(*I, &II->get(X86::POP32r));
NumEmitted++; // Keep track of the # of mi's emitted
}
-static unsigned sizeOfImm(const TargetInstrDescriptor *Desc) {
+static unsigned sizeOfImm(const TargetInstrDesc *Desc) {
switch (Desc->TSFlags & X86II::ImmMask) {
case X86II::Imm8: return 1;
case X86II::Imm16: return 2;
switch (Desc->TSFlags & X86II::ImmMask) {
case X86II::Imm8: return 1;
case X86II::Imm16: return 2;
/// size, and 3) use of X86-64 extended registers.
unsigned Emitter::determineREX(const MachineInstr &MI) {
unsigned REX = 0;
/// size, and 3) use of X86-64 extended registers.
unsigned Emitter::determineREX(const MachineInstr &MI) {
unsigned REX = 0;
- const TargetInstrDescriptor *Desc = MI.getDesc();
+ const TargetInstrDesc &Desc = MI.getDesc();
// Pseudo instructions do not need REX prefix byte.
// Pseudo instructions do not need REX prefix byte.
- if ((Desc->TSFlags & X86II::FormMask) == X86II::Pseudo)
+ if ((Desc.TSFlags & X86II::FormMask) == X86II::Pseudo)
- if (Desc->TSFlags & X86II::REX_W)
+ if (Desc.TSFlags & X86II::REX_W)
- unsigned NumOps = Desc->getNumOperands();
+ unsigned NumOps = Desc.getNumOperands();
if (NumOps) {
bool isTwoAddr = NumOps > 1 &&
if (NumOps) {
bool isTwoAddr = NumOps > 1 &&
- Desc->getOperandConstraint(1, TOI::TIED_TO) != -1;
+ Desc.getOperandConstraint(1, TOI::TIED_TO) != -1;
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
unsigned i = isTwoAddr ? 1 : 0;
// If it accesses SPL, BPL, SIL, or DIL, then it requires a 0x40 REX prefix.
unsigned i = isTwoAddr ? 1 : 0;
- switch (Desc->TSFlags & X86II::FormMask) {
+ switch (Desc.TSFlags & X86II::FormMask) {
case X86II::MRMInitReg:
if (isX86_64ExtendedReg(MI.getOperand(0)))
REX |= (1 << 0) | (1 << 2);
case X86II::MRMInitReg:
if (isX86_64ExtendedReg(MI.getOperand(0)))
REX |= (1 << 0) | (1 << 2);
}
void Emitter::emitInstruction(const MachineInstr &MI,
}
void Emitter::emitInstruction(const MachineInstr &MI,
- const TargetInstrDescriptor *Desc) {
+ const TargetInstrDesc *Desc) {
unsigned Opcode = Desc->Opcode;
// Emit the repeat opcode prefix as needed.
unsigned Opcode = Desc->Opcode;
// Emit the repeat opcode prefix as needed.
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
for (MachineBasicBlock::iterator I = BB.begin(); I != BB.end(); ++I) {
MachineInstr *MI = I;
- unsigned Flags = MI->getDesc()->TSFlags;
+ unsigned Flags = MI->getDesc().TSFlags;
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
if ((Flags & X86II::FPTypeMask) == X86II::NotFP)
continue; // Efficiently ignore non-fp insts!
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
///
void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- unsigned NumOps = MI->getDesc()->getNumOperands();
+ unsigned NumOps = MI->getDesc().getNumOperands();
assert((NumOps == 5 || NumOps == 1) &&
"Can only handle fst* & ftst instructions!");
assert((NumOps == 5 || NumOps == 1) &&
"Can only handle fst* & ftst instructions!");
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
///
void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) {
MachineInstr *MI = I;
- unsigned NumOps = MI->getDesc()->getNumOperands();
+ unsigned NumOps = MI->getDesc().getNumOperands();
assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
// Is this the last use of the source register?
assert(NumOps >= 2 && "FPRW instructions must have 2 ops!!");
// Is this the last use of the source register?
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
- unsigned NumOperands = MI->getDesc()->getNumOperands();
+ unsigned NumOperands = MI->getDesc().getNumOperands();
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
unsigned Dest = getFPReg(MI->getOperand(0));
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
assert(NumOperands == 3 && "Illegal TwoArgFP instruction!");
unsigned Dest = getFPReg(MI->getOperand(0));
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
ASSERT_SORTED(ForwardSTiTable); ASSERT_SORTED(ReverseSTiTable);
MachineInstr *MI = I;
- unsigned NumOperands = MI->getDesc()->getNumOperands();
+ unsigned NumOperands = MI->getDesc().getNumOperands();
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
assert(NumOperands == 2 && "Illegal FUCOM* instruction!");
unsigned Op0 = getFPReg(MI->getOperand(NumOperands-2));
unsigned Op1 = getFPReg(MI->getOperand(NumOperands-1));
}
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
}
bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
- const TargetInstrDescriptor *TID = MI->getDesc();
- if (!TID->isTerminator()) return false;
+ const TargetInstrDesc &TID = MI->getDesc();
+ if (!TID.isTerminator()) return false;
// Conditional branch is a special case.
// Conditional branch is a special case.
- if (TID->isBranch() && !TID->isBarrier())
+ if (TID.isBranch() && !TID.isBarrier())
- if (!TID->isPredicable())
+ if (!TID.isPredicable())
return true;
return !isPredicated(MI);
}
return true;
return !isPredicated(MI);
}
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
// If there is only one terminator instruction, process it.
if (I == MBB.begin() || !isBrAnalysisUnpredicatedTerminator(--I, *this)) {
- if (!LastInst->getDesc()->isBranch())
+ if (!LastInst->getDesc().isBranch())
return true;
// If the block ends with a branch there are 3 possibilities:
return true;
// If the block ends with a branch there are 3 possibilities:
MIB.addImm(1).addReg(0).addImm(0);
// Loop over the rest of the ri operands, converting them over.
MIB.addImm(1).addReg(0).addImm(0);
// Loop over the rest of the ri operands, converting them over.
- unsigned NumOps = MI->getDesc()->getNumOperands()-2;
+ unsigned NumOps = MI->getDesc().getNumOperands()-2;
for (unsigned i = 0; i != NumOps; ++i) {
MachineOperand &MO = MI->getOperand(i+2);
MIB = X86InstrAddOperand(MIB, MO);
for (unsigned i = 0; i != NumOps; ++i) {
MachineOperand &MO = MI->getOperand(i+2);
MIB = X86InstrAddOperand(MIB, MO);
SmallVector<MachineOperand,4> &MOs) const {
const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
bool isTwoAddrFold = false;
SmallVector<MachineOperand,4> &MOs) const {
const DenseMap<unsigned*, unsigned> *OpcodeTablePtr = NULL;
bool isTwoAddrFold = false;
- unsigned NumOps = MI->getDesc()->getNumOperands();
+ unsigned NumOps = MI->getDesc().getNumOperands();
bool isTwoAddr = NumOps > 1 &&
bool isTwoAddr = NumOps > 1 &&
- MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
+ MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
MachineInstr *NewMI = NULL;
// Folding a memory location into the two-address part of a two-address
MachineInstr *NewMI = NULL;
// Folding a memory location into the two-address part of a two-address
return NULL;
SmallVector<MachineOperand,4> MOs;
return NULL;
SmallVector<MachineOperand,4> MOs;
- unsigned NumOps = LoadMI->getDesc()->getNumOperands();
+ unsigned NumOps = LoadMI->getDesc().getNumOperands();
for (unsigned i = NumOps - 4; i != NumOps; ++i)
MOs.push_back(LoadMI->getOperand(i));
return foldMemoryOperand(MI, Ops[0], MOs);
for (unsigned i = NumOps - 4; i != NumOps; ++i)
MOs.push_back(LoadMI->getOperand(i));
return foldMemoryOperand(MI, Ops[0], MOs);
unsigned OpNum = Ops[0];
unsigned Opc = MI->getOpcode();
unsigned OpNum = Ops[0];
unsigned Opc = MI->getOpcode();
- unsigned NumOps = MI->getDesc()->getNumOperands();
+ unsigned NumOps = MI->getDesc().getNumOperands();
bool isTwoAddr = NumOps > 1 &&
bool isTwoAddr = NumOps > 1 &&
- MI->getDesc()->getOperandConstraint(1, TOI::TIED_TO) != -1;
+ MI->getDesc().getOperandConstraint(1, TOI::TIED_TO) != -1;
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
// Folding a memory location into the two-address part of a two-address
// instruction is different than folding it other places. It requires
return false;
UnfoldStore &= FoldedStore;
return false;
UnfoldStore &= FoldedStore;
- const TargetInstrDescriptor &TID = get(Opc);
+ const TargetInstrDesc &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
unsigned Index = I->second.second & 0xf;
bool FoldedLoad = I->second.second & (1 << 4);
bool FoldedStore = I->second.second & (1 << 5);
unsigned Index = I->second.second & 0xf;
bool FoldedLoad = I->second.second & (1 << 4);
bool FoldedStore = I->second.second & (1 << 5);
- const TargetInstrDescriptor &TID = get(Opc);
+ const TargetInstrDesc &TID = get(Opc);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
const TargetOperandInfo &TOI = TID.OpInfo[Index];
const TargetRegisterClass *RC = TOI.isLookupPtrRegClass()
? getPointerRegClass() : RI.getRegClass(TOI.RegClass);
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
// specified machine instruction.
//
// getBaseOpcodeFor - This function returns the "base" X86 opcode for the
// specified machine instruction.
//
- unsigned char getBaseOpcodeFor(const TargetInstrDescriptor *TID) const {
+ unsigned char getBaseOpcodeFor(const TargetInstrDesc *TID) const {
return TID->TSFlags >> X86II::OpcodeShift;
}
unsigned char getBaseOpcodeFor(unsigned Opcode) const {
return TID->TSFlags >> X86II::OpcodeShift;
}
unsigned char getBaseOpcodeFor(unsigned Opcode) const {
MachineBasicBlock::iterator PI = prior(MBBI);
unsigned Opc = PI->getOpcode();
if (Opc != X86::POP32r && Opc != X86::POP64r &&
MachineBasicBlock::iterator PI = prior(MBBI);
unsigned Opc = PI->getOpcode();
if (Opc != X86::POP32r && Opc != X86::POP64r &&
- !PI->getDesc()->isTerminator())
+ !PI->getDesc().isTerminator())
// Emit all of the operand info records.
EmitOperandInfo(OS, OperandInfoIDs);
// Emit all of the operand info records.
EmitOperandInfo(OS, OperandInfoIDs);
- // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
+ // Emit all of the TargetInstrDesc records in their ENUM ordering.
- OS << "\nstatic const TargetInstrDescriptor " << TargetName
+ OS << "\nstatic const TargetInstrDesc " << TargetName
<< "Insts[] = {\n";
std::vector<const CodeGenInstruction*> NumberedInstructions;
Target.getInstructionsByEnumValue(NumberedInstructions);
<< "Insts[] = {\n";
std::vector<const CodeGenInstruction*> NumberedInstructions;
Target.getInstructionsByEnumValue(NumberedInstructions);
projects / oota-llvm.git / commitdiff