DAGCombiner: don't optimise non-existant litpool load

This particular DAG combine is designed to kick in when both ConstantFPs will
end up being loaded via a litpool, however those nodes have a semi-legal
status, dictated by isFPImmLegal so in some cases there wouldn't have been a
litpool in the first place. Don't try to be clever in those circumstances.

Picked up while merging some AArch64 tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206365 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index b6b0341dc936208f0dd8724980ff5d4faada112e..1a92c2f59a9dbc94900eb14deb05c0655542ea75 100644 (file)
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -10942,7 +10942,9 @@ SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
     if (ConstantFPSDNode *FV = dyn_cast<ConstantFPSDNode>(N3)) {
       if (TLI.isTypeLegal(N2.getValueType()) &&
           (TLI.getOperationAction(ISD::ConstantFP, N2.getValueType()) !=
-           TargetLowering::Legal) &&
+               TargetLowering::Legal &&
+           !TLI.isFPImmLegal(TV->getValueAPF(), TV->getValueType(0)) &&
+           !TLI.isFPImmLegal(FV->getValueAPF(), FV->getValueType(0))) &&
           // If both constants have multiple uses, then we won't need to do an
           // extra load, they are likely around in registers for other users.
           (TV->hasOneUse() || FV->hasOneUse())) {

diff --git a/test/CodeGen/AArch64/regress-f128csel-flags.ll b/test/CodeGen/AArch64/regress-f128csel-flags.ll
index b35185ccd6f3e40ffc10a909d7d5f9eac7000f9c..a7352d6815eed1e60b82aa9d9928b36a655ca480 100644 (file)
--- a/test/CodeGen/AArch64/regress-f128csel-flags.ll
+++ b/test/CodeGen/AArch64/regress-f128csel-flags.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=arm64-none-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s
 
 ; We used to not mark NZCV as being used in the continuation basic-block
 ; when lowering a 128-bit "select" to branches. This meant a subsequent use

diff --git a/test/CodeGen/ARM64/fcmp-opt.ll b/test/CodeGen/ARM64/fcmp-opt.ll
index 17412dde742e95f96d489211d3782b002fec47c3..a90dabb4a4bcc50c76dd949d6fbb8a1978db0834 100644 (file)
--- a/test/CodeGen/ARM64/fcmp-opt.ll
+++ b/test/CodeGen/ARM64/fcmp-opt.ll
@@ -3,7 +3,7 @@
 
 define i1 @fcmp_float1(float %a) nounwind ssp {
 entry:
-; CHECK: @fcmp_float1
+; CHECK-LABEL: @fcmp_float1
 ; CHECK: fcmp s0, #0.0
 ; CHECK: csinc w0, wzr, wzr, eq
   %cmp = fcmp une float %a, 0.000000e+00
@@ -12,7 +12,7 @@ entry:
 
 define i1 @fcmp_float2(float %a, float %b) nounwind ssp {
 entry:
-; CHECK: @fcmp_float2
+; CHECK-LABEL: @fcmp_float2
 ; CHECK: fcmp s0, s1
 ; CHECK: csinc w0, wzr, wzr, eq
   %cmp = fcmp une float %a, %b
@@ -21,7 +21,7 @@ entry:
 
 define i1 @fcmp_double1(double %a) nounwind ssp {
 entry:
-; CHECK: @fcmp_double1
+; CHECK-LABEL: @fcmp_double1
 ; CHECK: fcmp d0, #0.0
 ; CHECK: csinc w0, wzr, wzr, eq
   %cmp = fcmp une double %a, 0.000000e+00
@@ -30,7 +30,7 @@ entry:
 
 define i1 @fcmp_double2(double %a, double %b) nounwind ssp {
 entry:
-; CHECK: @fcmp_double2
+; CHECK-LABEL: @fcmp_double2
 ; CHECK: fcmp d0, d1
 ; CHECK: csinc w0, wzr, wzr, eq
   %cmp = fcmp une double %a, %b
@@ -39,108 +39,137 @@ entry:
 
 ; Check each fcmp condition
 define float @fcmp_oeq(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_oeq
+; CHECK-LABEL: @fcmp_oeq
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ne
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], eq
+
   %cmp = fcmp oeq float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_ogt(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ogt
+; CHECK-LABEL: @fcmp_ogt
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, le
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], gt
+
   %cmp = fcmp ogt float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_oge(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_oge
+; CHECK-LABEL: @fcmp_oge
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, lt
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ge
+
   %cmp = fcmp oge float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_olt(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_olt
+; CHECK-LABEL: @fcmp_olt
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, pl
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], mi
+
   %cmp = fcmp olt float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_ole(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ole
+; CHECK-LABEL: @fcmp_ole
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, hi
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ls
+
   %cmp = fcmp ole float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_ord(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ord
+; CHECK-LABEL: @fcmp_ord
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, vs
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vc
   %cmp = fcmp ord float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_uno(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_uno
+; CHECK-LABEL: @fcmp_uno
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, vc
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], vs
   %cmp = fcmp uno float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_ugt(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ugt
+; CHECK-LABEL: @fcmp_ugt
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ls
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], hi
   %cmp = fcmp ugt float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_uge(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_uge
+; CHECK-LABEL: @fcmp_uge
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, mi
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], pl
   %cmp = fcmp uge float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_ult(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ult
+; CHECK-LABEL: @fcmp_ult
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, ge
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], lt
   %cmp = fcmp ult float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_ule(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ule
+; CHECK-LABEL: @fcmp_ule
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, gt
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], le
   %cmp = fcmp ule float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
 }
 
 define float @fcmp_une(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_une
+; CHECK-LABEL: @fcmp_une
 ; CHECK: fcmp s0, s1
-; CHECK: csinc w{{[0-9]+}}, wzr, wzr, eq
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel s0, s[[ONE]], s[[ZERO]], ne
   %cmp = fcmp une float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
@@ -149,11 +178,12 @@ define float @fcmp_une(float %a, float %b) nounwind ssp {
 ; Possible opportunity for improvement.  See comment in
 ; ARM64TargetLowering::LowerSETCC()
 define float @fcmp_one(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_one
+; CHECK-LABEL: @fcmp_one
 ;      fcmp    s0, s1
-;      orr     w0, wzr, #0x1
-;      csel    w1, w0, wzr, mi
-;      csel    w0, w0, wzr, gt
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel [[TMP:s[0-9]+]], s[[ONE]], s[[ZERO]], mi
+; CHECK: fcsel s0, s[[ONE]], [[TMP]], gt
   %cmp = fcmp one float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv
@@ -162,11 +192,12 @@ define float @fcmp_one(float %a, float %b) nounwind ssp {
 ; Possible opportunity for improvement.  See comment in
 ; ARM64TargetLowering::LowerSETCC()
 define float @fcmp_ueq(float %a, float %b) nounwind ssp {
-; CHECK: @fcmp_ueq
+; CHECK-LABEL: @fcmp_ueq
 ; CHECK: fcmp s0, s1
-;        orr w0, wzr, #0x1
-; CHECK: csel [[REG1:w[0-9]]], [[REG2:w[0-9]+]], wzr, eq
-; CHECK: csel {{w[0-9]+}}, [[REG2]], [[REG1]], vs
+; CHECK-DAG: movi.2d v[[ZERO:[0-9]+]], #0
+; CHECK-DAG: fmov s[[ONE:[0-9]+]], #1.0
+; CHECK: fcsel [[TMP:s[0-9]+]], s[[ONE]], s[[ZERO]], eq
+; CHECK: fcsel s0, s[[ONE]], [[TMP]], vs
   %cmp = fcmp ueq float %a, %b
   %conv = uitofp i1 %cmp to float
   ret float %conv