ARM two-operand aliases for VRHADD instructions.

rdar://11252521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154832 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index c7219a60f6c38fdd4a47bfd89bae15611a8d5516..e4106aa5cccaa413da0e5f1e620aa95beba7b12a 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -6951,6 +6951,38 @@ def : NEONInstAlias<"vsli${p}.32 $Vdm, $imm",
 def : NEONInstAlias<"vsli${p}.64 $Vdm, $imm",
                     (VSLIv2i64 QPR:$Vdm, QPR:$Vdm, shr_imm64:$imm, pred:$p)>;
 
+
+// Two-operand variants for VRHADD.
+    // Signed.
+def : NEONInstAlias<"vrhadd${p}.s8 $Vdn, $Rm",
+                    (VRHADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
+def : NEONInstAlias<"vrhadd${p}.s16 $Vdn, $Rm",
+                    (VRHADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
+def : NEONInstAlias<"vrhadd${p}.s32 $Vdn, $Rm",
+                    (VRHADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
+
+def : NEONInstAlias<"vrhadd${p}.s8 $Vdn, $Rm",
+                    (VRHADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
+def : NEONInstAlias<"vrhadd${p}.s16 $Vdn, $Rm",
+                    (VRHADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
+def : NEONInstAlias<"vrhadd${p}.s32 $Vdn, $Rm",
+                    (VRHADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
+
+    // Unsigned.
+def : NEONInstAlias<"vrhadd${p}.u8 $Vdn, $Rm",
+                    (VRHADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
+def : NEONInstAlias<"vrhadd${p}.u16 $Vdn, $Rm",
+                    (VRHADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
+def : NEONInstAlias<"vrhadd${p}.u32 $Vdn, $Rm",
+                    (VRHADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Rm, pred:$p)>;
+
+def : NEONInstAlias<"vrhadd${p}.u8 $Vdn, $Rm",
+                    (VRHADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
+def : NEONInstAlias<"vrhadd${p}.u16 $Vdn, $Rm",
+                    (VRHADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
+def : NEONInstAlias<"vrhadd${p}.u32 $Vdn, $Rm",
+                    (VRHADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Rm, pred:$p)>;
+
 // VSWP allows, but does not require, a type suffix.
 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
                          (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;

diff --git a/test/MC/ARM/neon-add-encoding.s b/test/MC/ARM/neon-add-encoding.s
index aeb4823e94b3e9b1d71f1604914c7df046bbcc72..280082ab1bf2e31466bd3515001741a380cf54b0 100644 (file)
--- a/test/MC/ARM/neon-add-encoding.s
+++ b/test/MC/ARM/neon-add-encoding.s
@@ -77,6 +77,19 @@
        vrhadd.u8       q8, q8, q9
        vrhadd.u16      q8, q8, q9
        vrhadd.u32      q8, q8, q9
+        @ Two-operand forms.
+       vrhadd.s8       d16, d17
+       vrhadd.s16      d16, d17
+       vrhadd.s32      d16, d17
+       vrhadd.u8       d16, d17
+       vrhadd.u16      d16, d17
+       vrhadd.u32      d16, d17
+       vrhadd.s8       q8, q9
+       vrhadd.s16      q8, q9
+       vrhadd.s32      q8, q9
+       vrhadd.u8       q8, q9
+       vrhadd.u16      q8, q9
+       vrhadd.u32      q8, q9
 
 @ CHECK: vrhadd.s8     d16, d16, d17   @ encoding: [0xa1,0x01,0x40,0xf2]
 @ CHECK: vrhadd.s16    d16, d16, d17   @ encoding: [0xa1,0x01,0x50,0xf2]
@@ -91,6 +104,20 @@
 @ CHECK: vrhadd.u16    q8, q8, q9      @ encoding: [0xe2,0x01,0x50,0xf3]
 @ CHECK: vrhadd.u32    q8, q8, q9      @ encoding: [0xe2,0x01,0x60,0xf3]
 
+@ CHECK: vrhadd.s8     d16, d16, d17   @ encoding: [0xa1,0x01,0x40,0xf2]
+@ CHECK: vrhadd.s16    d16, d16, d17   @ encoding: [0xa1,0x01,0x50,0xf2]
+@ CHECK: vrhadd.s32    d16, d16, d17   @ encoding: [0xa1,0x01,0x60,0xf2]
+@ CHECK: vrhadd.u8     d16, d16, d17   @ encoding: [0xa1,0x01,0x40,0xf3]
+@ CHECK: vrhadd.u16    d16, d16, d17   @ encoding: [0xa1,0x01,0x50,0xf3]
+@ CHECK: vrhadd.u32    d16, d16, d17   @ encoding: [0xa1,0x01,0x60,0xf3]
+@ CHECK: vrhadd.s8     q8, q8, q9      @ encoding: [0xe2,0x01,0x40,0xf2]
+@ CHECK: vrhadd.s16    q8, q8, q9      @ encoding: [0xe2,0x01,0x50,0xf2]
+@ CHECK: vrhadd.s32    q8, q8, q9      @ encoding: [0xe2,0x01,0x60,0xf2]
+@ CHECK: vrhadd.u8     q8, q8, q9      @ encoding: [0xe2,0x01,0x40,0xf3]
+@ CHECK: vrhadd.u16    q8, q8, q9      @ encoding: [0xe2,0x01,0x50,0xf3]
+@ CHECK: vrhadd.u32    q8, q8, q9      @ encoding: [0xe2,0x01,0x60,0xf3]
+
+
        vqadd.s8        d16, d16, d17
        vqadd.s16       d16, d16, d17
        vqadd.s32       d16, d16, d17