Fix a bug that prevented x86-64 from using rep.movsq for

8-byte-aligned data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49571 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 1ab272781b266581f328c8727b85fb5fd199961c..66384f921c2b7cfd0e23e20af1d11926055f2569 100644 (file)
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4621,7 +4621,7 @@ SDOperand X86TargetLowering::LowerMEMSET(SDOperand Op, SelectionDAG &DAG) {
         ValReg = X86::EAX;
         Val = (Val << 8)  | Val;
         Val = (Val << 16) | Val;
-        if (Subtarget->is64Bit() && ((Align & 0xF) == 0)) {  // QWORD aligned
+        if (Subtarget->is64Bit() && ((Align & 0x7) == 0)) {  // QWORD aligned
           AVT = MVT::i64;
           ValReg = X86::RAX;
           Val = (Val << 32) | Val;
@@ -4740,7 +4740,7 @@ SDOperand X86TargetLowering::LowerMEMCPYInline(SDOperand Chain,
       break;
     case 0:  // DWORD aligned
       AVT = MVT::i32;
-      if (Subtarget->is64Bit() && ((Align & 0xF) == 0))  // QWORD aligned
+      if (Subtarget->is64Bit() && ((Align & 0x7) == 0))  // QWORD aligned
         AVT = MVT::i64;
       break;
     default:  // Byte aligned

diff --git a/test/CodeGen/X86/byval2.ll b/test/CodeGen/X86/byval2.ll
index d017aa5fa33bc1d0079d7e6f089dccbcaf857478..f438160bdaabd4beb2b2aec5a2eef213bfd8dc82 100644 (file)
--- a/test/CodeGen/X86/byval2.ll
+++ b/test/CodeGen/X86/byval2.ll
@@ -1,4 +1,4 @@
-; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsl | count 2
+; RUN: llvm-as < %s | llc -march=x86-64 | grep rep.movsq | count 2
 ; RUN: llvm-as < %s | llc -march=x86    | grep rep.movsl | count 2
 
 %struct.s = type { i64, i64, i64 }