[arm fast-isel] Appease the machine verifier by using the proper register

classes.  The vast majority of the remaining issues are due to uses of
invalid registers, which are defined by getRegForValue().  Those will be
a little more challenging to cleanup.
rdar://12719844

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168735 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp
index e972a93687cb927e17445e80e821d37d9e46ee9d..8d88f9416bf63deb90f6f4f04dfdba4df2aa0ca3 100644 (file)
--- a/lib/Target/ARM/ARMFastISel.cpp
+++ b/lib/Target/ARM/ARMFastISel.cpp
@@ -2586,26 +2586,24 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
   default: return 0;
   case MVT::i16:
     if (!Subtarget->hasV6Ops()) return 0;
-    if (isZExt) {
+    RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
+    if (isZExt)
       Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
-    } else {
+    else
       Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
-      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
-    }
     break;
   case MVT::i8:
     if (!Subtarget->hasV6Ops()) return 0;
-    if (isZExt) {
+    RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
+    if (isZExt)
       Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
-    } else {
+    else
       Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
-      RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
-    }
     break;
   case MVT::i1:
     if (isZExt) {
-      Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
       RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
+      Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
       isBoolZext = true;
       break;
     }