Reversed the order of the llvm.writeport() operands so that the value

is listed first and the address is listed second.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12795 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp
index ce86e9cd94f0127b54707a87e0638578033b52d7..7a1f54e6061bfae23048e3f9114675b520482980 100644 (file)
--- a/lib/Target/X86/InstSelectSimple.cpp
+++ b/lib/Target/X86/InstSelectSimple.cpp
@@ -1702,7 +1702,7 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
     // acceptable range for this architecture.
     //
     //
     // acceptable range for this architecture.
     //
     //

-    if ((CI.getOperand(1)->getType()->getPrimitiveSize()) != 2) {
+    if ((CI.getOperand(2)->getType()->getPrimitiveSize()) != 2) {

       std::cerr << "llvm.writeport: Address size is not 16 bits\n";
       exit (1);
     }
       std::cerr << "llvm.writeport: Address size is not 16 bits\n";
       exit (1);
     }


@@ -1711,18 +1711,18 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
     // Now, move the I/O port address into the DX register and the value to
     // write into the AL/AX/EAX register.
     //
     // Now, move the I/O port address into the DX register and the value to
     // write into the AL/AX/EAX register.
     //

-    BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
-    switch (CI.getOperand(2)->getType()->getPrimitiveSize()) {
+    BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(2)));
+    switch (CI.getOperand(1)->getType()->getPrimitiveSize()) {

       case 1:
       case 1:

-        BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2)));
+        BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(1)));

         BuildMI(BB, X86::OUT8, 0);
         break;
       case 2:
         BuildMI(BB, X86::OUT8, 0);
         break;
       case 2:

-        BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2)));
+        BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(1)));

         BuildMI(BB, X86::OUT16, 0);
         break;
       case 4:
         BuildMI(BB, X86::OUT16, 0);
         break;
       case 4:

-        BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2)));
+        BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(1)));

         BuildMI(BB, X86::OUT32, 0);
         break;
       default:
         BuildMI(BB, X86::OUT32, 0);
         break;
       default:

diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp
index ce86e9cd94f0127b54707a87e0638578033b52d7..7a1f54e6061bfae23048e3f9114675b520482980 100644 (file)
--- a/lib/Target/X86/X86ISelSimple.cpp
+++ b/lib/Target/X86/X86ISelSimple.cpp
@@ -1702,7 +1702,7 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
     // acceptable range for this architecture.
     //
     //
     // acceptable range for this architecture.
     //
     //

-    if ((CI.getOperand(1)->getType()->getPrimitiveSize()) != 2) {
+    if ((CI.getOperand(2)->getType()->getPrimitiveSize()) != 2) {

       std::cerr << "llvm.writeport: Address size is not 16 bits\n";
       exit (1);
     }
       std::cerr << "llvm.writeport: Address size is not 16 bits\n";
       exit (1);
     }


@@ -1711,18 +1711,18 @@ void ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
     // Now, move the I/O port address into the DX register and the value to
     // write into the AL/AX/EAX register.
     //
     // Now, move the I/O port address into the DX register and the value to
     // write into the AL/AX/EAX register.
     //

-    BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(1)));
-    switch (CI.getOperand(2)->getType()->getPrimitiveSize()) {
+    BuildMI(BB, X86::MOV16rr, 1, X86::DX).addReg(getReg(CI.getOperand(2)));
+    switch (CI.getOperand(1)->getType()->getPrimitiveSize()) {

       case 1:
       case 1:

-        BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(2)));
+        BuildMI(BB, X86::MOV8rr, 1, X86::AL).addReg(getReg(CI.getOperand(1)));

         BuildMI(BB, X86::OUT8, 0);
         break;
       case 2:
         BuildMI(BB, X86::OUT8, 0);
         break;
       case 2:

-        BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(2)));
+        BuildMI(BB, X86::MOV16rr, 1, X86::AX).addReg(getReg(CI.getOperand(1)));

         BuildMI(BB, X86::OUT16, 0);
         break;
       case 4:
         BuildMI(BB, X86::OUT16, 0);
         break;
       case 4:

-        BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(2)));
+        BuildMI(BB, X86::MOV32rr, 1, X86::EAX).addReg(getReg(CI.getOperand(1)));

         BuildMI(BB, X86::OUT32, 0);
         break;
       default:
         BuildMI(BB, X86::OUT32, 0);
         break;
       default:

diff --git a/lib/VMCore/Verifier.cpp b/lib/VMCore/Verifier.cpp
index 73192eb77f3f9668aabb70994c04fd996b29b532..f40ffe0a13bf0fc2bd8c1f93e0efa520bcf17ca5 100644 (file)
--- a/lib/VMCore/Verifier.cpp
+++ b/lib/VMCore/Verifier.cpp
@@ -611,9 +611,9 @@ void Verifier::visitIntrinsicFunctionCall(Intrinsic::ID ID, CallInst &CI) {
   case Intrinsic::writeport:
     Assert1(FT->getNumParams() == 2,
             "Illegal # arguments for intrinsic function!", IF);
   case Intrinsic::writeport:
     Assert1(FT->getNumParams() == 2,
             "Illegal # arguments for intrinsic function!", IF);

-    Assert1(FT->getParamType(0)->isUnsigned(),
+    Assert1(FT->getParamType(0)->isIntegral(),

             "First argument not unsigned int!", IF);
             "First argument not unsigned int!", IF);

-    Assert1(FT->getParamType(1)->isIntegral(),
+    Assert1(FT->getParamType(1)->isUnsigned(),

             "First argument not unsigned int!", IF);
     NumArgs = 2;
     break;
             "First argument not unsigned int!", IF);
     NumArgs = 2;
     break;