[PowerPC] Fix v2f64 vector extract and related patterns

First, v2f64 vector extract had not been declared legal (and so the existing
patterns were not being used). Second, the patterns for that, and for
scalar_to_vector, should really be a regclass copy, not a subregister
operation, because the VSX registers directly hold both the vector and scalar data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204971 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 16ff0eb7d726b9bd246a3abde4e4b5e51fcdaf84..1c19160c9c61db4d9e44012c7fdcc4c3e2c148f5 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -535,6 +535,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
 
     if (Subtarget->hasVSX()) {
       setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
+      setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
 
       setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
       setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);

diff --git a/lib/Target/PowerPC/PPCInstrVSX.td b/lib/Target/PowerPC/PPCInstrVSX.td
index 643ba1fbb02484784d46a10ea964e3140a9d7ae0..1ece55977a12bfb15b96efd074dfb782d58a9fad 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrVSX.td
+++ b/lib/Target/PowerPC/PPCInstrVSX.td
@@ -724,13 +724,12 @@ def : InstAlias<"xxswapd $XT, $XB",
 
 let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
 def : Pat<(v2f64 (scalar_to_vector f64:$A)),
-          (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), $A, sub_64)>;
+          (v2f64 (COPY_TO_REGCLASS $A, VSRC))>;
 
 def : Pat<(f64 (vector_extract v2f64:$S, 0)),
-          (EXTRACT_SUBREG (v2f64 (COPY_TO_REGCLASS $S, VSLRC)), sub_64)>;
+          (f64 (COPY_TO_REGCLASS $S, VSRC))>;
 def : Pat<(f64 (vector_extract v2f64:$S, 1)),
-          (EXTRACT_SUBREG (v2f64 (COPY_TO_REGCLASS (XXPERMDI $S, $S, 3),
-                                                   VSLRC)), sub_64)>;
+          (f64 (COPY_TO_REGCLASS (XXPERMDI $S, $S, 2), VSRC))>;
 
 // Additional fnmsub patterns: -a*c + b == -(a*c - b)
 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),

diff --git a/test/CodeGen/PowerPC/vsx.ll b/test/CodeGen/PowerPC/vsx.ll
index 89499560b341ec957fe5e0697c21cdfe3ac4b0a8..4f4f816d7237d20c14ca2b6d6bd8e59941dd69db 100644 (file)
--- a/test/CodeGen/PowerPC/vsx.ll
+++ b/test/CodeGen/PowerPC/vsx.ll
@@ -529,3 +529,21 @@ define <2 x i64> @test62(<2 x i64> %a, <2 x i64> %b) {
 ; CHECK: blr
 }
 
+define double @test63(<2 x double> %a) {
+  %v = extractelement <2 x double> %a, i32 0
+  ret double %v
+
+; CHECK-LABEL: @test63
+; CHECK: xxlor 1, 34, 34
+; CHECK: blr
+}
+
+define double @test64(<2 x double> %a) {
+  %v = extractelement <2 x double> %a, i32 1
+  ret double %v
+
+; CHECK-LABEL: @test64
+; CHECK: xxpermdi 1, 34, 34, 2
+; CHECK: blr
+}
+