int regNum; // register number for an explicit register
// will be set for a value after reg allocation
private:
- MachineOperand(int64_t ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister)
+ MachineOperand(int ImmVal = 0, MachineOperandType OpTy = MO_VirtualRegister)
: immedVal(ImmVal),
flags(0),
opType(OpTy),
assert(opType == MO_MachineRegister);
return regNum;
}
- int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
- void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; }
+ int getImmedValue() const { assert(isImmediate()); return immedVal; }
+ void setImmedValue(int ImmVal) { assert(isImmediate()); immedVal = ImmVal; }
MachineBasicBlock *getMachineBasicBlock() const {
assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
/// addZeroExtImmOperand - Add a zero extended constant argument to the
/// machine instruction.
///
- void addZeroExtImmOperand(int64_t intValue) {
+ void addZeroExtImmOperand(int intValue) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(
/// addSignExtImmOperand - Add a zero extended constant argument to the
/// machine instruction.
///
- void addSignExtImmOperand(int64_t intValue) {
+ void addSignExtImmOperand(int intValue) {
assert(!OperandsComplete() &&
"Trying to add an operand to a machine instr that is already done!");
operands.push_back(
// Access to set the operands when building the machine instruction
//
- void SetMachineOperandVal (unsigned i,
- MachineOperand::MachineOperandType operandType,
- Value* V);
+ void SetMachineOperandVal(unsigned i,
+ MachineOperand::MachineOperandType operandType,
+ Value* V);
- void SetMachineOperandConst (unsigned i,
- MachineOperand::MachineOperandType operandType,
- int64_t intValue);
+ void SetMachineOperandConst(unsigned i,
+ MachineOperand::MachineOperandType operandType,
+ int intValue);
void SetMachineOperandReg(unsigned i, int regNum);
/// addMReg - Add a machine register operand...
///
- const MachineInstrBuilder &addMReg(
- int Reg,
- MachineOperand::UseType Ty = MachineOperand::Use) const {
+ const MachineInstrBuilder &addMReg(int Reg, MachineOperand::UseType Ty
+ = MachineOperand::Use) const {
MI->addMachineRegOperand(Reg, Ty);
return *this;
}
+
+ /// addImm - Add a new immediate operand.
+ ///
+ const MachineInstrBuilder &addImm(int Val) const {
+ MI->addZeroExtImmOperand(Val);
+ return *this;
+ }
/// addSImm - Add a new sign extended immediate operand...
///
- const MachineInstrBuilder &addSImm(int64_t val) const {
+ const MachineInstrBuilder &addSImm(int val) const {
MI->addSignExtImmOperand(val);
return *this;
}
/// addZImm - Add a new zero extended immediate operand...
///
- const MachineInstrBuilder &addZImm(int64_t Val) const {
+ const MachineInstrBuilder &addZImm(unsigned Val) const {
MI->addZeroExtImmOperand(Val);
return *this;
}