MC/ARM/AsmParser: Minor nitty fixes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123175 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index ed664e9554752f1cdb403d9d47d42a8a8b64a9e0..d53ce935607c12ba11a2a6e070fc713d601b2b99 100644 (file)
--- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -26,7 +26,7 @@
 #include "llvm/ADT/Twine.h"
 using namespace llvm;
 
-// The shift types for register controlled shifts in arm memory addressing
+/// Shift types used for register controlled shifts in ARM memory addressing.
 enum ShiftType {
   Lsl,
   Lsr,
@@ -134,7 +134,7 @@ class ARMOperand : public MCParsedAsmOperand {
       const MCExpr *Val;
     } Imm;
 
-    // This is for all forms of ARM address expressions
+    /// Combined record for all forms of ARM address expressions.
     struct {
       unsigned BaseRegNum;
       unsigned OffsetRegNum;         // used when OffsetIsReg is true
@@ -436,7 +436,7 @@ public:
 void ARMOperand::dump(raw_ostream &OS) const {
   switch (Kind) {
   case CondCode:
-    OS << ARMCondCodeToString(getCondCode());
+    OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">";
     break;
   case CCOut:
     OS << "<ccout " << getReg() << ">";