Summary:
The analysis of shader inputs was completely wrong. We were passing the
wrong index to AttributeSet::hasAttribute() and the logic for which
inputs where in SGPRs was wrong too.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D15608
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256082
91177308-0d34-0410-b5e6-
96231b3b80d8
if (ShaderType == ShaderType::COMPUTE)
return true;
if (ShaderType == ShaderType::COMPUTE)
return true;
- // For non-compute shaders, the inreg attribute is used to mark inputs,
- // which pre-loaded into SGPRs.
- if (F->getAttributes().hasAttribute(A->getArgNo(), Attribute::InReg))
+ // For non-compute shaders, SGPR inputs are marked with either inreg or byval.
+ if (F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::InReg) ||
+ F->getAttributes().hasAttribute(A->getArgNo() + 1, Attribute::ByVal))
- // For non-compute shaders, 32-bit values are pre-loaded into vgprs, all
- // other value types use SGPRS.
- return !A->getType()->isIntegerTy(32) && !A->getType()->isFloatTy();
+ // Everything else is in VGPRs.
+ return false;
--- /dev/null
+; RUN: opt %s -mtriple amdgcn-- -analyze -divergence | FileCheck %s
+
+; CHECK: DIVERGENT:
+; CHECK-NOT: %arg0
+; CHECK-NOT: %arg1
+; CHECK-NOT; %arg2
+; CHECK: <2 x i32> %arg3
+; CHECK: DIVERGENT: <3 x i32> %arg4
+; CHECK: DIVERGENT: float %arg5
+; CHECK: DIVERGENT: i32 %arg6
+
+define void @main([4 x <16 x i8>] addrspace(2)* byval %arg0, float inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <3 x i32> %arg4, float %arg5, i32 %arg6) #0 {
+ ret void
+}
+
+attributes #0 = { "ShaderType"="0" }
--- /dev/null
+if not 'AMDGPU' in config.root.targets:
+ config.unsupported = True