Fix order of operands on a store from reg to [reg+offset].

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4857 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 9b7256f9e64cc9c0605f7b214681871324e02a30..4ec2971070060dfda1fbb770bbcee6fd5d331f35 100644 (file)
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -31,8 +31,8 @@ X86RegisterInfo::storeReg2RegOffset(MachineBasicBlock *MBB,
                                     unsigned ImmOffset, unsigned dataSize)
   const
 {
-  MachineInstr *MI = addRegOffset(BuildMI(X86::MOVrm32, 5).addReg(SrcReg),
-                                  DestReg, ImmOffset);
+  MachineInstr *MI = addRegOffset(BuildMI(X86::MOVrm32, 5),
+                                  DestReg, ImmOffset).addReg(SrcReg);
   return ++(MBB->insert(MBBI, MI));
 }