Changed definition of EXT and INS per Bruno's comments.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137892 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp
index 2ac7a266db829994b9df2d94f8aeff6f9a14395b..cbd1f3edc7504a2135bb9aa6ab5e4314b685ee71 100644 (file)
--- a/lib/Target/Mips/MipsISelLowering.cpp
+++ b/lib/Target/Mips/MipsISelLowering.cpp
@@ -558,8 +558,8 @@ static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
 
   return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
                      ShiftRight.getOperand(0),
-                     DAG.getConstant(SMSize, MVT::i32),
-                     DAG.getConstant(Pos, MVT::i32));
+                     DAG.getConstant(Pos, MVT::i32),
+                     DAG.getConstant(SMSize, MVT::i32));
 }
   
 static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
@@ -613,8 +613,8 @@ static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
   
   return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
                      Shl.getOperand(0),
-                     DAG.getConstant(SMSize0, MVT::i32),
                      DAG.getConstant(SMPos0, MVT::i32),
+                     DAG.getConstant(SMSize0, MVT::i32),
                      And0.getOperand(0));  
 }
   

diff --git a/lib/Target/Mips/MipsInstrFormats.td b/lib/Target/Mips/MipsInstrFormats.td
index fd6422048d9ad35b5aae47f33bf898b2bb41f888..9f55fb38b959c23f908593e52deae3ae862135a2 100644 (file)
--- a/lib/Target/Mips/MipsInstrFormats.td
+++ b/lib/Target/Mips/MipsInstrFormats.td
@@ -102,28 +102,6 @@ class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
   let Inst{25-0} = addr;
 }
 
-// Ext and Ins
-class ExtIns<bits<6> _funct, string instr_asm, dag Outs, dag Ins,
-             list<dag> pattern, InstrItinClass itin>:
-  MipsInst<Outs, Ins, !strconcat(instr_asm, "\t$dst, $src, $pos, $size"),
-           pattern, itin>
-{
-  bits<5>  rt;
-  bits<5>  rs;
-  bits<5>  sz;
-  bits<5>  pos;
-  bits<6>  funct;
-
-  let opcode = 0x1f;
-  let funct  = _funct;
-
-  let Inst{25-21} = rs;
-  let Inst{20-16} = rt;
-  let Inst{15-11} = sz;
-  let Inst{10-6}  = pos;
-  let Inst{5-0}   = funct;
-}
-
 //===----------------------------------------------------------------------===//
 //
 //  FLOATING POINT INSTRUCTION FORMATS

diff --git a/lib/Target/Mips/MipsInstrInfo.td b/lib/Target/Mips/MipsInstrInfo.td
index e41c78ab4589ec23ac0b48694f30fe7e650f3ecf..0ead91bd32525e36034041fcf85459aecf5336e8 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.td
+++ b/lib/Target/Mips/MipsInstrInfo.td
@@ -405,6 +405,19 @@ class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src),
   let shamt = 0;
 }
 
+// Ext and Ins
+class ExtIns<bits<6> _funct, string instr_asm, dag ins,
+             list<dag> pattern, InstrItinClass itin>:
+  FR<0x1f, _funct, (outs CPURegs:$rt), ins,
+     !strconcat(instr_asm, "\t$rt, $rs, $pos, $size"), pattern, itin> {
+  bits<5> src;
+  bits<5> pos;
+  bits<5> size;
+  let rs = src;
+  let rd = size;
+  let shamt = pos;
+}
+
 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
 class Atomic2Ops<PatFrag Op, string Opstr> :
   MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
@@ -677,20 +690,19 @@ def MUL   : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[IsMips32]>;
 def RDHWR : ReadHardware;
 
 let Predicates = [IsMips32r2] in {
-  def Ext : ExtIns<0b000000, "ext", (outs CPURegs:$dst),
-                   (ins CPURegs:$src, uimm16:$size, uimm16:$pos),
-                   [(set CPURegs:$dst,
-                     (MipsExt CPURegs:$src, immZExt5:$size, immZExt5:$pos))],
-                   NoItinerary>;
-  let Constraints = "$src1 = $dst" in
-  def Ins : ExtIns<0b000100, "ins",
-                   (outs CPURegs:$dst),
-                   (ins CPURegs:$src, uimm16:$size, uimm16:$pos,
-                    CPURegs:$src1),
-                   [(set CPURegs:$dst,
-                     (MipsIns CPURegs:$src, immZExt5:$size, immZExt5:$pos,
-                      CPURegs:$src1))],
-                   NoItinerary>;
+
+def EXT : ExtIns<0, "ext", (ins CPURegs:$rs, uimm16:$pos, uimm16:$size),
+                 [(set CPURegs:$rt, 
+                   (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
+                 NoItinerary>;
+
+let Constraints = "$src = $rt" in
+def INS : ExtIns<4, "ins",
+                 (ins CPURegs:$rs, uimm16:$pos, uimm16:$size, CPURegs:$src),
+                 [(set CPURegs:$rt, 
+                   (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$size,
+                    CPURegs:$src))],
+                 NoItinerary>;
 }
 
 //===----------------------------------------------------------------------===//