Provide proper stack offsets for outgoing arguments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75945 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp
index 937c4c858c657507197203148ced91dbd68cced1..c8ad01758cc29f0af4f42274c6083daa6649f8cb 100644 (file)
--- a/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -38,6 +38,8 @@ using namespace llvm;
 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
   TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
 
+  RegInfo = TM.getRegisterInfo();
+
   // Set up the register classes.
   addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
   addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
@@ -190,6 +192,7 @@ SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
   SDValue Callee = TheCall->getCallee();
   bool isVarArg  = TheCall->isVarArg();
   DebugLoc dl = Op.getDebugLoc();
+  MachineFunction &MF = DAG.getMachineFunction();
 
   // Analyze operands of the call, assigning locations to each operand.
   SmallVector<CCValAssign, 16> ArgLocs;
@@ -237,12 +240,16 @@ SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
       assert(VA.isMemLoc());
 
       if (StackPtr.getNode() == 0)
-        StackPtr = DAG.getCopyFromReg(Chain, dl, SystemZ::R15D, getPointerTy());
-
-      SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
-                                   StackPtr,
-                                   DAG.getIntPtrConstant(VA.getLocMemOffset()));
-
+        StackPtr =
+          DAG.getCopyFromReg(Chain, dl,
+                             (RegInfo->hasFP(MF) ?
+                              SystemZ::R11D : SystemZ::R15D),
+                             getPointerTy());
+
+      SDValue PtrOff =
+        DAG.getNode(ISD::ADD, dl, getPointerTy(),
+                    StackPtr,
+                    DAG.getIntPtrConstant(160+VA.getLocMemOffset()));
 
       MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
                                          PseudoSourceValue::getStack(),

diff --git a/lib/Target/SystemZ/SystemZISelLowering.h b/lib/Target/SystemZ/SystemZISelLowering.h
index 760a51d8dd5a8f0d4127a3411d199e2871c4b355..4e74b972430f79d70150853fe4276e823aa8923b 100644 (file)
--- a/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/lib/Target/SystemZ/SystemZISelLowering.h
@@ -16,6 +16,7 @@
 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
 
 #include "SystemZ.h"
+#include "SystemZRegisterInfo.h"
 #include "llvm/CodeGen/SelectionDAG.h"
 #include "llvm/Target/TargetLowering.h"
 
@@ -61,6 +62,7 @@ namespace llvm {
   private:
     const SystemZSubtarget &Subtarget;
     const SystemZTargetMachine &TM;
+    const SystemZRegisterInfo *RegInfo;
   };
 } // namespace llvm
 

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.h b/lib/Target/SystemZ/SystemZInstrInfo.h
index 1e0cc82c69b49454ec11054e662bb8fae143dcd5..6bc9f37393235c8f047a857b403e832610cb8505 100644 (file)
--- a/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -33,7 +33,7 @@ public:
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).
   ///
-  virtual const TargetRegisterInfo &getRegisterInfo() const { return RI; }
+  virtual const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
 
   bool copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                     unsigned DestReg, unsigned SrcReg,

diff --git a/lib/Target/SystemZ/SystemZTargetMachine.h b/lib/Target/SystemZ/SystemZTargetMachine.h
index 194d5fe016cfc1954a460c624370cb20b2e8a8e1..4862a99b4cc6b6531c07c76378b230a6cfa27308 100644 (file)
--- a/lib/Target/SystemZ/SystemZTargetMachine.h
+++ b/lib/Target/SystemZ/SystemZTargetMachine.h
@@ -48,7 +48,7 @@ public:
   virtual const TargetData *getTargetData() const     { return &DataLayout;}
   virtual const SystemZSubtarget *getSubtargetImpl() const { return &Subtarget; }
 
-  virtual const TargetRegisterInfo *getRegisterInfo() const {
+  virtual const SystemZRegisterInfo *getRegisterInfo() const {
     return &InstrInfo.getRegisterInfo();
   }