Fix a problem where lib/Target/TargetInstrInfo.h would include and use

a header file from libcodegen.  This violates a layering order: codegen
depends on target, not the other way around.  The fix to this is to
split TII into two classes, TII and TargetInstrInfoImpl, which defines
stuff that depends on libcodegen.  It is defined in libcodegen, where
the base is not.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45475 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h
index a02e1e11803bacb8a5028c58782dc28e0d040c86..9a96eb5b381f35d77ee0bdb53eb1eceb4b26c8ab 100644 (file)
--- a/include/llvm/Target/TargetInstrInfo.h
+++ b/include/llvm/Target/TargetInstrInfo.h
@@ -406,7 +406,7 @@ public:
   /// return a new machine instruction.  If an instruction cannot commute, it
   /// can also return null.
   ///
-  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
+  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const = 0;
 
   /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
   /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
@@ -504,7 +504,7 @@ public:
   /// instruction. It returns true if the operation was successful.
   virtual
   bool PredicateInstruction(MachineInstr *MI,
-                            const std::vector<MachineOperand> &Pred) const;
+                            const std::vector<MachineOperand> &Pred) const = 0;
 
   /// SubsumesPredicate - Returns true if the first specified predicate
   /// subsumes the second, e.g. GE subsumes GT.
@@ -531,6 +531,21 @@ public:
   }
 };
 
+/// TargetInstrInfoImpl - This is the default implementation of
+/// TargetInstrInfo, which just provides a couple of default implementations
+/// for various methods.  This separated out because it is implemented in
+/// libcodegen, not in libtarget.
+class TargetInstrInfoImpl : public TargetInstrInfo {
+protected:
+  TargetInstrInfoImpl(const TargetInstrDescriptor *desc, unsigned NumOpcodes)
+  : TargetInstrInfo(desc, NumOpcodes) {}
+public:
+  virtual MachineInstr *commuteInstruction(MachineInstr *MI) const;
+  virtual bool PredicateInstruction(MachineInstr *MI,
+                              const std::vector<MachineOperand> &Pred) const;
+  
+};
+
 } // End llvm namespace
 
 #endif

diff --git a/lib/CodeGen/TargetInstrInfoImpl.cpp b/lib/CodeGen/TargetInstrInfoImpl.cpp
new file mode 100644 (file)
index 0000000..18cc303
--- /dev/null
+++ b/lib/CodeGen/TargetInstrInfoImpl.cpp
@@ -0,0 +1,58 @@
+//===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file implements the TargetInstrInfoImpl class, it just provides default
+// implementations of various methods.
+//
+//===----------------------------------------------------------------------===//
+
+#include "llvm/Target/TargetInstrInfo.h"
+#include "llvm/CodeGen/MachineInstr.h"
+using namespace llvm;
+
+// commuteInstruction - The default implementation of this method just exchanges
+// operand 1 and 2.
+MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI) const {
+  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
+         "This only knows how to commute register operands so far");
+  unsigned Reg1 = MI->getOperand(1).getReg();
+  unsigned Reg2 = MI->getOperand(2).getReg();
+  bool Reg1IsKill = MI->getOperand(1).isKill();
+  bool Reg2IsKill = MI->getOperand(2).isKill();
+  MI->getOperand(2).setReg(Reg1);
+  MI->getOperand(1).setReg(Reg2);
+  MI->getOperand(2).setIsKill(Reg1IsKill);
+  MI->getOperand(1).setIsKill(Reg2IsKill);
+  return MI;
+}
+
+bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
+                                               const std::vector<MachineOperand> &Pred) const {
+  bool MadeChange = false;
+  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
+  if (TID->Flags & M_PREDICABLE) {
+    for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
+      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
+        MachineOperand &MO = MI->getOperand(i);
+        if (MO.isReg()) {
+          MO.setReg(Pred[j].getReg());
+          MadeChange = true;
+        } else if (MO.isImm()) {
+          MO.setImm(Pred[j].getImm());
+          MadeChange = true;
+        } else if (MO.isMBB()) {
+          MO.setMBB(Pred[j].getMBB());
+          MadeChange = true;
+        }
+        ++j;
+      }
+    }
+  }
+  return MadeChange;
+}

diff --git a/lib/Target/ARM/ARMInstrInfo.cpp b/lib/Target/ARM/ARMInstrInfo.cpp
index b2c064901e36487c8369ef2a748e90913317af3b..82756b61b12b04e881436b5cf5b292f9240db7d8 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/lib/Target/ARM/ARMInstrInfo.cpp
@@ -38,7 +38,7 @@ const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
 }
 
 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
-  : TargetInstrInfo(ARMInsts, array_lengthof(ARMInsts)),
+  : TargetInstrInfoImpl(ARMInsts, array_lengthof(ARMInsts)),
     RI(*this, STI) {
 }
 

diff --git a/lib/Target/ARM/ARMInstrInfo.h b/lib/Target/ARM/ARMInstrInfo.h
index 4951ad4ed99b1e91457b24cf814b35268af9dde8..4b000bb0d06e126f1d29b276e24e76a42968e521 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.h
+++ b/lib/Target/ARM/ARMInstrInfo.h
@@ -125,7 +125,7 @@ namespace ARMII {
   };
 }
 
-class ARMInstrInfo : public TargetInstrInfo {
+class ARMInstrInfo : public TargetInstrInfoImpl {
   const ARMRegisterInfo RI;
 public:
   ARMInstrInfo(const ARMSubtarget &STI);

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index db0dc7b2518303cac08790fcdb7da7ca88c31ebf..7a475b0f04bf9fd03ff7e2ae070c544726c41496 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -19,7 +19,7 @@
 using namespace llvm;
 
 AlphaInstrInfo::AlphaInstrInfo()
-  : TargetInstrInfo(AlphaInsts, array_lengthof(AlphaInsts)),
+  : TargetInstrInfoImpl(AlphaInsts, array_lengthof(AlphaInsts)),
     RI(*this) { }
 
 

diff --git a/lib/Target/Alpha/AlphaInstrInfo.h b/lib/Target/Alpha/AlphaInstrInfo.h
index 7ce377ad8ff8182f168fd84951a1e20f3bac3410..a7fd5455ac15063059ed556c58efde6af4958ce9 100644 (file)
--- a/lib/Target/Alpha/AlphaInstrInfo.h
+++ b/lib/Target/Alpha/AlphaInstrInfo.h
@@ -19,7 +19,7 @@
 
 namespace llvm {
 
-class AlphaInstrInfo : public TargetInstrInfo {
+class AlphaInstrInfo : public TargetInstrInfoImpl {
   const AlphaRegisterInfo RI;
 public:
   AlphaInstrInfo();

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index 0e5c5057281b0d5af723184568bef4f38047cd1a..5c520b46607239102e801348912463e05e123fed 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -21,7 +21,7 @@
 using namespace llvm;
 
 SPUInstrInfo::SPUInstrInfo(SPUTargetMachine &tm)
-  : TargetInstrInfo(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
+  : TargetInstrInfoImpl(SPUInsts, sizeof(SPUInsts)/sizeof(SPUInsts[0])),
     TM(tm),
     RI(*TM.getSubtargetImpl(), *this)
 {

diff --git a/lib/Target/CellSPU/SPUInstrInfo.h b/lib/Target/CellSPU/SPUInstrInfo.h
index e99865199e9d0b415e6802fc7c0aa1e195578b71..5132b3fa7ff40c70d55c9ee0452c070ded223a37 100644 (file)
--- a/lib/Target/CellSPU/SPUInstrInfo.h
+++ b/lib/Target/CellSPU/SPUInstrInfo.h
@@ -20,8 +20,7 @@
 
 namespace llvm {
   //! Cell SPU instruction information class
-  class SPUInstrInfo : public TargetInstrInfo
-  {
+  class SPUInstrInfo : public TargetInstrInfoImpl {
     SPUTargetMachine &TM;
     const SPURegisterInfo RI;
   public:

diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp
index ea3336cf16e6b6a3940c5820ab403b53e294bcd3..516f4a9c038de7734609f8943ff14962cd0580d4 100644 (file)
--- a/lib/Target/IA64/IA64InstrInfo.cpp
+++ b/lib/Target/IA64/IA64InstrInfo.cpp
@@ -19,7 +19,7 @@
 using namespace llvm;
 
 IA64InstrInfo::IA64InstrInfo()
-  : TargetInstrInfo(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
+  : TargetInstrInfoImpl(IA64Insts, sizeof(IA64Insts)/sizeof(IA64Insts[0])),
     RI(*this) {
 }
 

diff --git a/lib/Target/IA64/IA64InstrInfo.h b/lib/Target/IA64/IA64InstrInfo.h
index 07a98a5a567cd5908e05a6e1e60bc9981cc6f119..826c7a97f3b462bb5145960b09638ea7f5fdd69b 100644 (file)
--- a/lib/Target/IA64/IA64InstrInfo.h
+++ b/lib/Target/IA64/IA64InstrInfo.h
@@ -19,7 +19,7 @@
 
 namespace llvm {
 
-class IA64InstrInfo : public TargetInstrInfo {
+class IA64InstrInfo : public TargetInstrInfoImpl {
   const IA64RegisterInfo RI;
 public:
   IA64InstrInfo();

diff --git a/lib/Target/Mips/MipsInstrInfo.cpp b/lib/Target/Mips/MipsInstrInfo.cpp
index 17d30b608bd13bf92e589ef37eac0e07a72fe4d1..4f6a1f04c1bc1c42cc739f91cbdcc74127556ae3 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.cpp
+++ b/lib/Target/Mips/MipsInstrInfo.cpp
@@ -21,7 +21,7 @@ using namespace llvm;
 
 // TODO: Add the subtarget support on this constructor
 MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
-  : TargetInstrInfo(MipsInsts, array_lengthof(MipsInsts)),
+  : TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
     TM(tm), RI(*this) {}
 
 static bool isZeroImm(const MachineOperand &op) {

diff --git a/lib/Target/Mips/MipsInstrInfo.h b/lib/Target/Mips/MipsInstrInfo.h
index ee63a4a86e02577734c407c50d40523f2cdfd1ac..22164a63e5219bb2372277ea2fc7f664eff0e237 100644 (file)
--- a/lib/Target/Mips/MipsInstrInfo.h
+++ b/lib/Target/Mips/MipsInstrInfo.h
@@ -42,8 +42,7 @@ namespace Mips {
 
 }
 
-class MipsInstrInfo : public TargetInstrInfo 
-{
+class MipsInstrInfo : public TargetInstrInfoImpl {
   MipsTargetMachine &TM;
   const MipsRegisterInfo RI;
 public:

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 327622f32fd7c9c939b95bda58dbddc088133c7a..9982f907b35f247d2df4636bdd6c59c6d3901cbc 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -20,7 +20,7 @@
 using namespace llvm;
 
 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
-  : TargetInstrInfo(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
+  : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
     RI(*TM.getSubtargetImpl(), *this) {}
 
 /// getPointerRegClass - Return the register class to use to hold pointers.

diff --git a/lib/Target/PowerPC/PPCInstrInfo.h b/lib/Target/PowerPC/PPCInstrInfo.h
index f511e23d211464f4eacd45a829220c79165c5dd6..ac3cf558fb15f5fa3b647b5297a06da58eb91fb0 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.h
+++ b/lib/Target/PowerPC/PPCInstrInfo.h
@@ -61,7 +61,7 @@ enum PPC970_Unit {
 }
   
   
-class PPCInstrInfo : public TargetInstrInfo {
+class PPCInstrInfo : public TargetInstrInfoImpl {
   PPCTargetMachine &TM;
   const PPCRegisterInfo RI;
 public:

diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index 5a64a4428c680721eabd1c4ae4e3540db2d06782..7b2914c085dbe2fb0543c21eed13489cff8e53f1 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -20,7 +20,7 @@
 using namespace llvm;
 
 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
-  : TargetInstrInfo(SparcInsts, array_lengthof(SparcInsts)),
+  : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
     RI(ST, *this), Subtarget(ST) {
 }
 

diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h
index 16540abb56c9001f8ef3abd5c9aa49b6c6b07432..46a6a8f3a13150aacb2b181126793da855795233 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.h
+++ b/lib/Target/Sparc/SparcInstrInfo.h
@@ -31,7 +31,7 @@ namespace SPII {
   };
 }
 
-class SparcInstrInfo : public TargetInstrInfo {
+class SparcInstrInfo : public TargetInstrInfoImpl {
   const SparcRegisterInfo RI;
   const SparcSubtarget& Subtarget;
 public:

diff --git a/lib/Target/TargetInstrInfo.cpp b/lib/Target/TargetInstrInfo.cpp
index 9849c7564eecaa5f7a1d1f65b6772a62763bb620..d8d1578c72def0ce2e21f7e5461fe46ace0c3cc8 100644 (file)
--- a/lib/Target/TargetInstrInfo.cpp
+++ b/lib/Target/TargetInstrInfo.cpp
@@ -12,7 +12,6 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/Constant.h"
 #include "llvm/DerivedTypes.h"
 using namespace llvm;
@@ -38,47 +37,6 @@ TargetInstrInfo::TargetInstrInfo(const TargetInstrDescriptor* Desc,
 TargetInstrInfo::~TargetInstrInfo() {
 }
 
-// commuteInstruction - The default implementation of this method just exchanges
-// operand 1 and 2.
-MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
-  assert(MI->getOperand(1).isRegister() && MI->getOperand(2).isRegister() &&
-         "This only knows how to commute register operands so far");
-  unsigned Reg1 = MI->getOperand(1).getReg();
-  unsigned Reg2 = MI->getOperand(2).getReg();
-  bool Reg1IsKill = MI->getOperand(1).isKill();
-  bool Reg2IsKill = MI->getOperand(2).isKill();
-  MI->getOperand(2).setReg(Reg1);
-  MI->getOperand(1).setReg(Reg2);
-  MI->getOperand(2).setIsKill(Reg1IsKill);
-  MI->getOperand(1).setIsKill(Reg2IsKill);
-  return MI;
-}
-
-bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
-                                const std::vector<MachineOperand> &Pred) const {
-  bool MadeChange = false;
-  const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
-  if (TID->Flags & M_PREDICABLE) {
-    for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
-      if ((TID->OpInfo[i].Flags & M_PREDICATE_OPERAND)) {
-        MachineOperand &MO = MI->getOperand(i);
-        if (MO.isReg()) {
-          MO.setReg(Pred[j].getReg());
-          MadeChange = true;
-        } else if (MO.isImm()) {
-          MO.setImm(Pred[j].getImm());
-          MadeChange = true;
-        } else if (MO.isMBB()) {
-          MO.setMBB(Pred[j].getMBB());
-          MadeChange = true;
-        }
-        ++j;
-      }
-    }
-  }
-  return MadeChange;
-}
-
 bool TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
   const TargetInstrDescriptor *TID = MI->getInstrDescriptor();
   if (TID->Flags & M_TERMINATOR_FLAG) {

diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 76979d8e1b12004a8d6e490b0fd411cc4ecf5a63..e12f646a883516922ddb9636ed85094c0d1c07c1 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -25,7 +25,7 @@
 using namespace llvm;
 
 X86InstrInfo::X86InstrInfo(X86TargetMachine &tm)
-  : TargetInstrInfo(X86Insts, array_lengthof(X86Insts)),
+  : TargetInstrInfoImpl(X86Insts, array_lengthof(X86Insts)),
     TM(tm), RI(tm, *this) {
 }
 

diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h
index 88df88295162dc8efdbd31d814d74ec267eef239..e6ca781714fce8c3dc1d26ae7b551a881882380e 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.h
+++ b/lib/Target/X86/X86InstrInfo.h
@@ -222,7 +222,7 @@ namespace X86II {
   };
 }
 
-class X86InstrInfo : public TargetInstrInfo {
+class X86InstrInfo : public TargetInstrInfoImpl {
   X86TargetMachine &TM;
   const X86RegisterInfo RI;
   mutable IndexedMap<const MachineInstr*, VirtReg2IndexFunctor> MachineInstrMap;