Detect FI|cst pattern in MipsDAGToDAGISel::SelectAddr. Patch by Sasa Stankovic.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132448 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index b2aba2730540e99defeada31f422e9f8be042347..c0c1c30753e3f1036199c1d999b52afd9863c9bd 100644 (file)
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -135,24 +135,25 @@ SelectAddr(SDValue Addr, SDValue &Offset, SDValue &Base) {
     }
   }
 
-  // Operand is a result from an ADD.
-  if (Addr.getOpcode() == ISD::ADD) {
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
-      if (isInt<16>(CN->getSExtValue())) {
-
-        // If the first operand is a FI, get the TargetFI Node
-        if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
-                                    (Addr.getOperand(0))) {
-          Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
-        } else {
-          Base = Addr.getOperand(0);
-        }
-
-        Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
-        return true;
-      }
+  // Addresses of the form FI+const or FI|const
+  if (CurDAG->isBaseWithConstantOffset(Addr)) {
+    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
+    if (isInt<16>(CN->getSExtValue())) {
+
+      // If the first operand is a FI, get the TargetFI Node
+      if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
+                                  (Addr.getOperand(0)))
+        Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
+      else
+        Base = Addr.getOperand(0);
+
+      Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
+      return true;
     }
+  }
 
+  // Operand is a result from an ADD.
+  if (Addr.getOpcode() == ISD::ADD) {
     // When loading from constant pools, load the lower address part in
     // the instruction itself. Example, instead of:
     //  lui $2, %hi($CPI1_0)

diff --git a/test/CodeGen/Mips/largeimmprinting.ll b/test/CodeGen/Mips/largeimmprinting.ll
index fcc20f799440ffb99b1d7222fe5fdd13d319233a..fd7ae9e0ac20df4091ae24c5a69b8fa769b62661 100644 (file)
--- a/test/CodeGen/Mips/largeimmprinting.ll
+++ b/test/CodeGen/Mips/largeimmprinting.ll
@@ -8,7 +8,7 @@ define void @f() nounwind {
 entry:
 ; CHECK:  lui $at, 65534
 ; CHECK:  addu  $at, $sp, $at
-; CHECK:  addiu $sp, $at, -24
+; CHECK:  addiu $sp, $at, -16
 ; CHECK:  .cprestore  65536
 
   %agg.tmp = alloca %struct.S1, align 1

diff --git a/test/CodeGen/Mips/o32_cc_byval.ll b/test/CodeGen/Mips/o32_cc_byval.ll
index f504bd7d55938f1a18e6eb78345181504e27af91..b78c393498c4bf231dce91877772ec117540c7df 100644 (file)
--- a/test/CodeGen/Mips/o32_cc_byval.ll
+++ b/test/CodeGen/Mips/o32_cc_byval.ll
@@ -10,18 +10,16 @@
 
 define void @f1() nounwind {
 entry:
-; CHECK: lw  $[[R0:[0-9]+]], %got(f1.s1)($gp)
-; CHECK: addiu $[[R1:[0-9]+]], $sp, 16
-; CHECK: addiu $[[R0:[0-9]+]], $[[R0]], %lo(f1.s1)
+; CHECK: lw  $[[R1:[0-9]+]], %got(f1.s1)($gp)
+; CHECK: addiu $[[R0:[0-9]+]], $[[R1]], %lo(f1.s1)
 ; CHECK: lw  $[[R2:[0-9]+]], 8($[[R0]])
+; CHECK: lw  $[[R7:[0-9]+]], 12($[[R0]])
 ; CHECK: lw  $[[R3:[0-9]+]], 16($[[R0]])
 ; CHECK: lw  $[[R4:[0-9]+]], 20($[[R0]])
 ; CHECK: lw  $[[R5:[0-9]+]], 24($[[R0]])
 ; CHECK: lw  $[[R6:[0-9]+]], 28($[[R0]])
-; CHECK: lw  $[[R7:[0-9]+]], 12($[[R0]])
-; CHECK: ori $[[R8:[0-9]+]], $[[R1]], 4
 ; CHECK: sw  $[[R2]], 16($sp)
-; CHECK: sw  $[[R7]], 0($[[R8]])
+; CHECK: sw  $[[R7]], 20($sp)
 ; CHECK: sw  $[[R3]], 24($sp)
 ; CHECK: sw  $[[R4]], 28($sp)
 ; CHECK: sw  $[[R5]], 32($sp)
@@ -46,14 +44,11 @@ declare void @callee3(float, %struct.S3* byval, %struct.S1* byval)
 define void @f2(float %f, %struct.S1* nocapture byval %s1) nounwind {
 entry:
 ; CHECK: addiu $sp, $sp, -56
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
-; CHECK: ori $[[R1:[0-9]+]], $[[R0]], 4
-; CHECK: ori $[[R0:[0-9]+]], $[[R0]], 2
 ; CHECK: sw  $6, 64($sp)
-; CHECK: sw  $7, 0($[[R1]])
+; CHECK: sw  $7, 68($sp)
 ; CHECK: ldc1 $f[[F0:[0-9]+]], 80($sp)
-; CHECK: lw  $[[R2:[0-9]+]], 0($[[R1]])
-; CHECK: lh  $[[R1:[0-9]+]], 0($[[R0]])
+; CHECK: lw  $[[R2:[0-9]+]], 68($sp)
+; CHECK: lh  $[[R1:[0-9]+]], 66($sp)
 ; CHECK: lb  $[[R0:[0-9]+]], 64($sp)
 ; CHECK: lw  $[[R3:[0-9]+]], 72($sp)
 ; CHECK: lw  $[[R4:[0-9]+]], 76($sp)
@@ -86,10 +81,8 @@ declare void @callee4(i32, double, i64, i32, i16 signext, i8 signext, float)
 define void @f3(%struct.S2* nocapture byval %s2) nounwind {
 entry:
 ; CHECK: addiu $sp, $sp, -56
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 56
-; CHECK: ori $[[R0:[0-9]+]], $[[R0]], 4
 ; CHECK: sw  $4, 56($sp)
-; CHECK: sw  $5, 0($[[R0]])
+; CHECK: sw  $5, 60($sp)
 ; CHECK: sw  $6, 64($sp)
 ; CHECK: sw  $7, 68($sp)
 ; CHECK: lw  $[[R0:[0-9]+]], 68($sp)
@@ -107,14 +100,12 @@ entry:
 define void @f4(float %f, %struct.S3* nocapture byval %s3, %struct.S1* nocapture byval %s1) nounwind {
 entry:
 ; CHECK: addiu $sp, $sp, -56
-; CHECK: addiu $[[R0:[0-9]+]], $sp, 64
-; CHECK: ori $[[R2:[0-9]+]], $[[R0]], 4
 ; CHECK: sw  $5, 60($sp)
 ; CHECK: sw  $6, 64($sp)
-; CHECK: sw  $7, 0($[[R2]])
+; CHECK: sw  $7, 68($sp)
 ; CHECK: lw  $[[R1:[0-9]+]], 88($sp)
 ; CHECK: lb  $[[R0:[0-9]+]], 60($sp)
-; CHECK: lw  $4, 0($[[R2]])
+; CHECK: lw  $4, 68($sp)
 ; CHECK: sw  $[[R1]], 24($sp)
 ; CHECK: sw  $[[R0]], 32($sp)