Take account of boolean vector contents when promoting a build vector from i1 to...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162960 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index e8e968aaef31991c65ce573a69779394766901de..cd93a511b66fa2258181d9be5ff28f5e02fbeb1d 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -2913,8 +2913,24 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BUILD_VECTOR(SDNode *N) {
 
   SmallVector<SDValue, 8> Ops;
   Ops.reserve(NumElems);
+  unsigned ExtendOp = ISD::ANY_EXTEND;
+  // Extending boolean constants needs to consider the
+  // value boolean vector constants take on this target and extend
+  // with sign or zeros appropriately.
+  if (OutVT.getVectorElementType() == MVT::i1) {
+    switch (TLI.getBooleanContents(true)) {
+      case TargetLowering::UndefinedBooleanContent:
+        break;
+      case TargetLowering::ZeroOrOneBooleanContent:
+      ExtendOp = ISD::ZERO_EXTEND;
+        break;
+      case TargetLowering::ZeroOrNegativeOneBooleanContent:
+        ExtendOp = ISD::SIGN_EXTEND;
+        break;
+    }
+  }
   for (unsigned i = 0; i != NumElems; ++i) {
-    SDValue Op = DAG.getNode(ISD::ANY_EXTEND, dl, NOutVTElem, N->getOperand(i));
+    SDValue Op = DAG.getNode(ExtendOp, dl, NOutVTElem, N->getOperand(i));
     Ops.push_back(Op);
   }
 

diff --git a/test/CodeGen/X86/vec_select.ll b/test/CodeGen/X86/vec_select.ll
new file mode 100644 (file)
index 0000000..065232c
--- /dev/null
+++ b/test/CodeGen/X86/vec_select.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march=x86 | FileCheck %s
+
+; When legalizing the v4i1 constant, we need to consider the boolean contents
+; For x86 a boolean vector constant is all ones so the constants in memory
+; will be ~0U not 1.
+
+; CHECK: .long 4294967295
+; CHECK: .long 4294967295
+; CHECK: .long 0
+; CHECK: .long 0
+
+; CHECK: test
+define <4 x i8> @test(<4 x i8> %a, <4 x i8> %b) {
+  %sel = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i8> %a, <4 x i8> %b
+       ret <4 x i8> %sel
+}