// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
// This is the top level entry point for the AArch64 target.
+//
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
//
-// AArch64 Assembly printer class.
+// This file defines the AArch64 assembly printer class.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
//
-//
+// This class implements the AArch64-specific parts of the TargetFrameLowering
+// class.
//
//===----------------------------------------------------------------------===//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+// This file describes AArch64 instruction formats, down to the level of the
+// instruction's overall class.
+// ===----------------------------------------------------------------------===//
+
//===----------------------------------------------------------------------===//
-//
// A64 Instruction Format Definitions.
-//
+//===----------------------------------------------------------------------===//
// A64 is currently the only instruction set supported by the AArch64
// architecture.
+//===----- AArch64InstrInfo.td - AArch64 Instruction Info ----*- tablegen -*-=//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the AArch64 scalar instructions in TableGen format.
+//
+//===----------------------------------------------------------------------===//
+
include "AArch64InstrFormats.td"
//===----------------------------------------------------------------------===//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-
+//
+// This file just contains the anchor for the AArch64MachineFunctionInfo to
+// force vtable emission.
+//
+//===----------------------------------------------------------------------===//
#include "AArch64MachineFunctionInfo.h"
using namespace llvm;
//
//===----------------------------------------------------------------------===//
//
-// This file contains the AArch64 implementation of the MRegisterInfo class.
+// This file contains the AArch64 implementation of the MCRegisterInfo class.
//
//===----------------------------------------------------------------------===//
-//===- ARMRegisterInfo.td - ARM Register defs --------------*- tablegen -*-===//
+//===- AArch64RegisterInfo.td - ARM Register defs ----------*- tablegen -*-===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Declarations that describe the ARM register file
+//
+// This file contains declarations that describe the AArch64 register file
+//
//===----------------------------------------------------------------------===//
let Namespace = "AArch64" in {
//
//===----------------------------------------------------------------------===//
//
+// This file contains the implementation of the AArch64TargetMachine
+// methods. Principally just setting up the passes needed to generate correct
+// code on this architecture.
//
//===----------------------------------------------------------------------===//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file deals with any AArch64 specific requirements on object files.
+//
+//===----------------------------------------------------------------------===//
+
#include "AArch64TargetObjectFile.h"
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file deals with any AArch64 specific requirements on object files.
+//
+//===----------------------------------------------------------------------===//
#ifndef LLVM_TARGET_AARCH64_TARGETOBJECTFILE_H
#define LLVM_TARGET_AARCH64_TARGETOBJECTFILE_H
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file contains the (GNU-style) assembly parser for the AArch64
+// architecture.
+//
+//===----------------------------------------------------------------------===//
#include "MCTargetDesc/AArch64MCTargetDesc.h"
-//===- AArch64Disassembler.cpp - Disassembler for AArch64/Thumb ISA -------===//
+//===- AArch64Disassembler.cpp - Disassembler for AArch64 ISA -------------===//
//
// The LLVM Compiler Infrastructure
//
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file contains the functions necessary to decode AArch64 instruction
+// bitpatterns into MCInsts (with the help of TableGenerated information from
+// the instruction definitions).
+//
+//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "arm-disassembler"
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file contains the AArch64 implementation of the MCAsmBackend class,
+// which is principally concerned with relaxation of the various fixup kinds.
+//
+//===----------------------------------------------------------------------===//
#include "MCTargetDesc/AArch64FixupKinds.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file handles ELF-specific object emission, converting LLVM's internal
+// fixups into the appropriate relocations.
+//
+//===----------------------------------------------------------------------===//
#include "MCTargetDesc/AArch64FixupKinds.h"
#include "MCTargetDesc/AArch64MCTargetDesc.h"
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file describes the LLVM fixups applied to MCInsts in the AArch64
+// backend.
+//
+//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64_AARCH64FIXUPKINDS_H
#define LLVM_AARCH64_AARCH64FIXUPKINDS_H
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file contains the implementation of the assembly expression modifiers
+// accepted by the AArch64 architecture (e.g. ":lo12:", ":gottprel_g1:", ...).
+//
+//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "aarch64mcexpr"
#include "AArch64MCExpr.h"
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file describes AArch64-specific MCExprs, used for modifiers like
+// ":lo12:" or ":gottprel_g1:".
+//
+//===----------------------------------------------------------------------===//
#ifndef LLVM_AARCH64MCEXPR_H
#define LLVM_AARCH64MCEXPR_H
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// This file contains the key registration step for the architecture.
+//
+//===----------------------------------------------------------------------===//
#include "AArch64.h"
#include "llvm/IR/Module.h"