temporarily revert r112664, it is causing a decoding conflict, and

the testcases should be merged.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112711 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 0353ea920a8fa0775b5d4f3de9bcb2ab311f01e2..4f4f4d08b41a5b0ab679946af6eb1f02c56eeda1 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -180,9 +180,6 @@ private:
   SDNode *SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
                                ARMCC::CondCodes CCVal, SDValue CCR,
                                SDValue InFlag);
-  SDNode *OptimizeCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
-                              ARMCC::CondCodes CCVal, SDValue CCR,
-                              SDValue InFlag, bool IsThumb2);
 
   SDNode *SelectConcatVector(SDNode *N);
 
@@ -1644,92 +1641,6 @@ SelectARMCMOVShiftOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
   return 0;
 }
 
-/// OptimizeCMOVSoImmOp - It's possible to save an instruction or two be
-/// recognizing that the TST and AND instructions perform the same function
-/// (they "and" the two values). See inside for more details.
-SDNode *ARMDAGToDAGISel::
-OptimizeCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
-                    ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag,
-                    bool IsThumb2) {
-  // Convert:
-  //
-  //   tst.w    r0, #256
-  //   mvn      r0, #25
-  //   it       eq
-  //   moveq    r0, #0
-  //
-  // into:
-  //
-  //   ands.w   r0, r0, #256
-  //   it       ne
-  //   mvnne.w  r0, #25
-  //
-  if (InFlag.getOpcode() != ARMISD::CMPZ ||
-      InFlag.getOperand(0).getOpcode() != ISD::AND)
-    return 0;
-
-  // The true value needs to be zero, as that's the result of the AND
-  // instruction.
-  ConstantSDNode *True = dyn_cast<ConstantSDNode>(TrueVal);
-  if (!True || True->getZExtValue() != 0)
-    return 0;
-
-  // Bail if the false value isn't an immediate.
-  ConstantSDNode *False = dyn_cast<ConstantSDNode>(FalseVal);
-  if (!False)
-    return 0;
-
-  bool UseMVN = false;
-  if ((IsThumb2 && !Pred_t2_so_imm(FalseVal.getNode())) ||
-      (!IsThumb2 && !Pred_so_imm(FalseVal.getNode()))) {
-    // The false value isn't a proper immediate. Check to see if we can use the
-    // bitwise NOT version.
-    if ((IsThumb2 && ARM_AM::getT2SOImmVal(~False->getZExtValue()) != -1) ||
-        (!IsThumb2 && ARM_AM::getSOImmVal(~False->getZExtValue()) != -1)) {
-      UseMVN = true;
-      FalseVal = CurDAG->getTargetConstant(~False->getZExtValue(), MVT::i32);
-    } else {
-      return 0;
-    }
-  } else {
-    FalseVal = CurDAG->getTargetConstant(False->getZExtValue(), MVT::i32);
-  }
-
-  // A comparison against zero corresponds with the flag AND sets if the result
-  // is zero.
-  ConstantSDNode *CmpVal = dyn_cast<ConstantSDNode>(InFlag.getOperand(1));
-  if (!CmpVal || CmpVal->getZExtValue() != 0)
-    return 0;
-
-  ARMCC::CondCodes NegCC = ARMCC::getOppositeCondition(CCVal);
-  SDValue OrigAnd = InFlag.getOperand(0);
-  SDValue NewAnd =
-    CurDAG->getNode(ARMISD::AND, N->getDebugLoc(),
-                    CurDAG->getVTList(OrigAnd.getValueType(), MVT::Flag),
-                    OrigAnd->getOperand(0), OrigAnd->getOperand(1));
-
-  unsigned Opcode = !UseMVN ?
-    (IsThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi) :
-    (IsThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi);
-
-  SDValue Ops[] = {
-    NewAnd.getValue(0),
-    FalseVal,
-    CurDAG->getTargetConstant(NegCC, MVT::i32),
-    CCR, NewAnd.getValue(1)
-  };
-  SDNode *ResNode = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, Ops, 5);
-
-  // Manually run "Select" on the newly created "ARMISD::AND" node to make
-  // sure that it's converted properly.
-  SDNode *AndNode = Select(NewAnd.getNode());
-  if (AndNode && NewAnd.getNode() != AndNode &&
-      NewAnd.getNode()->getOpcode() != ISD::DELETED_NODE)
-    ReplaceUses(NewAnd.getNode(), AndNode);
-
-  return ResNode;
-}
-
 SDNode *ARMDAGToDAGISel::
 SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
                     ARMCC::CondCodes CCVal, SDValue CCR, SDValue InFlag) {
@@ -1738,10 +1649,6 @@ SelectT2CMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
     return 0;
 
   if (Pred_t2_so_imm(TrueVal.getNode())) {
-    SDNode *ResNode = OptimizeCMOVSoImmOp(N, FalseVal, TrueVal, CCVal, CCR,
-                                          InFlag, true);
-    if (ResNode) return ResNode;
-
     SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
     SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
     SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
@@ -1759,10 +1666,6 @@ SelectARMCMOVSoImmOp(SDNode *N, SDValue FalseVal, SDValue TrueVal,
     return 0;
 
   if (Pred_so_imm(TrueVal.getNode())) {
-    SDNode *ResNode = OptimizeCMOVSoImmOp(N, FalseVal, TrueVal, CCVal, CCR,
-                                          InFlag, false);
-    if (ResNode) return ResNode;
-
     SDValue True = CurDAG->getTargetConstant(T->getZExtValue(), MVT::i32);
     SDValue CC = CurDAG->getTargetConstant(CCVal, MVT::i32);
     SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index d1d4390db07d7d1b3c216c41d1c51638e90cb261..e66f9b9ad0ac5653f03c881cd1ea688410fede12 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -2419,14 +2419,6 @@ def MOVCCi : AI1<0b1101, (outs GPR:$dst),
                 RegConstraint<"$false = $dst">, UnaryDP {
   let Inst{25} = 1;
 }
-
-def MVNCCi : AI1<0b1111, (outs GPR:$dst),
-                        (ins GPR:$false, so_imm:$true), DPFrm, IIC_iCMOVi,
-                "mvn", "\t$dst, $true",
-  [/*(set GPR:$dst, (ARMcmov GPR:$false,so_imm_not:$true,imm:$cc,CCR:$ccr))*/]>,
-                RegConstraint<"$false = $dst">, UnaryDP {
-  let Inst{25} = 0;
-}
 } // neverHasSideEffects
 
 //===----------------------------------------------------------------------===//

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index 270eeb5fdaf0fc0ed54e274acffe3b137c2be170..6ba0a44be4700b1811529b9aca2f5452ee4cf97e 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -2195,18 +2195,6 @@ def t2MOVCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
   let Inst{15} = 0;
 }
 
-def t2MVNCCi : T2I<(outs rGPR:$dst), (ins rGPR:$false, t2_so_imm:$true),
-                   IIC_iCMOVi, "mvn", ".w\t$dst, $true",
-[/*(set rGPR:$dst,(ARMcmov rGPR:$false,t2_so_imm_not:$true,imm:$cc,CCR:$ccr))*/]>,
-                   RegConstraint<"$false = $dst"> {
-  let Inst{31-27} = 0b11110;
-  let Inst{25} = 0;
-  let Inst{24-21} = 0b0011;
-  let Inst{20} = 0; // The S bit.
-  let Inst{19-16} = 0b1111; // Rn
-  let Inst{15} = 0;
-}
-
 class T2I_movcc_sh<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
                    string opc, string asm, list<dag> pattern>
   : T2I<oops, iops, itin, opc, asm, pattern> {

diff --git a/test/CodeGen/ARM/mvncc.ll b/test/CodeGen/ARM/mvncc.ll
deleted file mode 100644 (file)
index 4003a95..0000000
--- a/test/CodeGen/ARM/mvncc.ll
+++ /dev/null
@@ -1,12 +0,0 @@
-; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
-
-define i32 @f1(i32 %t) nounwind {
-; CHECK: f1
-; CHECK-NOT: tst
-; CHECK: and
-; CHECK: mvnne
-  %and = and i32 %t, 256
-  %tobool = icmp eq i32 %and, 0
-  %retval.0 = select i1 %tobool, i32 0, i32 -26
-  ret i32 %retval.0
-}

diff --git a/test/CodeGen/Thumb2/thumb2-mvncc.ll b/test/CodeGen/Thumb2/thumb2-mvncc.ll
deleted file mode 100644 (file)
index 893728b..0000000
--- a/test/CodeGen/Thumb2/thumb2-mvncc.ll
+++ /dev/null
@@ -1,13 +0,0 @@
-; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
-
-define i32 @f1(i32 %t) nounwind {
-; CHECK: f1
-; CHECK-NOT: tst
-; CHECK: ands
-; CHECK: it ne
-; CHECK: mvnne
-  %and = and i32 %t, 256
-  %tobool = icmp eq i32 %and, 0
-  %retval.0 = select i1 %tobool, i32 0, i32 -26
-  ret i32 %retval.0
-}