Add N3RegFrm to represent "NEON 3 vector register format" instructions.

Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector
Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99628 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td
index 1320bb4dca2af78002c7f711ff3102a80981fdfd..3504d0add32eac3033b2d2a5130c5773628233ea 100644 (file)
--- a/lib/Target/ARM/ARMInstrFormats.td
+++ b/lib/Target/ARM/ARMInstrFormats.td
@@ -66,6 +66,7 @@ def NVCVTFrm       : Format<34>;
 def NVDupLnFrm     : Format<35>;
 def N2RegVShLFrm   : Format<36>;
 def N2RegVShRFrm   : Format<37>;
+def N3RegFrm       : Format<38>;
 
 // Misc flags.
 
@@ -1606,7 +1607,7 @@ class N2VImm<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
 class N3V<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6, bit op4,
           dag oops, dag iops, InstrItinClass itin,
           string opc, string dt, string asm, string cstr, list<dag> pattern>
-  : NDataI<oops, iops, NEONFrm, itin, opc, dt, asm, cstr, pattern> {
+  : NDataI<oops, iops, N3RegFrm, itin, opc, dt, asm, cstr, pattern> {
   let Inst{24} = op24;
   let Inst{23} = op23;
   let Inst{21-20} = op21_20;
@@ -1620,7 +1621,7 @@ class N3VX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op6,
            bit op4,
            dag oops, dag iops, InstrItinClass itin,
            string opc, string asm, string cstr, list<dag> pattern>
-  : NDataXI<oops, iops, NEONFrm, itin, opc, asm, cstr, pattern> {
+  : NDataXI<oops, iops, N3RegFrm, itin, opc, asm, cstr, pattern> {
   let Inst{24} = op24;
   let Inst{23} = op23;
   let Inst{21-20} = op21_20;