Allow strict subclasses of register classes, this way we can handle

ARM instructions with:

foo GPR, rGPR

which happens a lot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112025 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp
index 243208612d5a9541a0ed6833b6d3bb0ce0a0e042..6c16fcfaa8a27aa621a869b36dd402b554274b33 100644 (file)
--- a/utils/TableGen/FastISelEmitter.cpp
+++ b/utils/TableGen/FastISelEmitter.cpp
@@ -112,9 +112,10 @@ struct OperandsSignature {
       if (!RC)
         return false;
 
-      // For now, all the operands must have the same register class.
+      // For now, all the operands must have the same register class or be
+      // a strict subclass of the destination.
       if (DstRC) {
-        if (DstRC != RC)
+        if (DstRC != RC && !DstRC->hasSubClass(RC))
           return false;
       } else
         DstRC = RC;